Method forming a semiconductor device structure having an underground interconnection embedded into a silicon substrate

Patent metadata

Field	Value
Publication number	US-12148500-B2
Application number	US-202217858986-A
Country	US
Kind code	B2
Filing date	Jul 6, 2022
Priority date	Dec 31, 2019
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

A semiconductor device structure includes a silicon substrate, a transistor, and an interconnection. The silicon substrate has a silicon surface. The transistor includes a gate structure, a first conductive region, a second conductive region, and a channel under the silicon surface. The interconnection is extended beyond the transistor and coupled to the first conductive region of the transistor. The interconnection is disposed under the silicon surface and isolated from the silicon substrate by an isolation region.

First claim

What is claimed is:

1. A method forming a semiconductor device structure comprising:
preparing a semiconductor substrate with an original surface;
based on the semiconductor substrate, forming a set of active regions and forming a shallow trench isolation between two active regions of the set of active regions;
forming a first interconnection layer within the shallow trench isolation and between the two active regions, wherein the first interconnection layer is disposed under the original surface of the semiconductor substrate;
depositing a first conductive material to form a second interconnection layer and a gate region of a transistor, wherein the gate region of the transistor is connected to the second interconnection layer and a part of the first conductive material is disposed in a concave within the active region; and
forming a connection plug within the active region to electrically connect the first interconnection layer to a first conductive region of the transistor;
wherein the first interconnection layer is isolated from the semiconductor substrate.

2. The method of claim 1 , the step of forming the set of active regions and the shallow trench isolation comprising:
depositing a pad-oxide layer and a pad-nitride layer to define the set of active regions;
etching the semiconductor substrate outside the active regions to create a trench between the two active regions; and
depositing an oxide layer in the trench to form the shallow trench isolation.

3. The method of claim 1 , the step of forming the first interconnection layer above the shallow trench isolation comprising:
forming asymmetrical spacers between the two active regions; and
form the first interconnection layer above the shallow trench isolation and between the asymmetrical spacers.

4. The method of claim 3 , the asymmetrical spacers includes an oxide spacer and a nitride spacer opposite to the oxide spacer.

5. The method of claim 3 , wherein the step of forming the connection plug comprising:
etching the one of the two active regions to create a hole and forming a dielectric layer in the hole;
removing a portion of the asymmetrical spacers to reveal a sidewall of the first interconnection layer;
depositing a second conductive material in the hole to contact the sidewall of the first interconnection layer;
removing an upper portion of the dielectric layer to reveal the first conductive region of the transistor; and
depositing a connection material to connect the first conductive region to the second conductive material;
wherein the connection plug comprises the connection material and the second conductive material.

6. The method of claim 1 , the step of forming the second interconnection layer and the gate region of the transistor comprising:
etching the one of the two active regions to create a concave therein; and
depositing a high-k insulator layer in the concave and depositing the first conductive material to form the second interconnection layer and the gate region of the transistor.

7. The method of claim 1 , further comprising:
forming a third interconnection to electrically connect a second conductive region of the transistor; wherein the third interconnection is deposited above the original surface of the semiconductor substrate.

8. The method of claim 1 , wherein the first interconnection layer is a bit line, and the transistor is an access transistor of a DRAM cell, and the second interconnection layer is a word line.

Assignees

• Etron Tech Inc
• Invent And Collaboration Laboratory Pte Ltd

Inventors

• Lu chao-chun
• Huang Li-Ping

Classifications

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10D62/116

  adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title