Integrated circuit and method of designing the same

Patent metadata

Field	Value
Publication number	US-12147751-B2
Application number	US-202117360355-A
Country	US
Kind code	B2
Filing date	Jun 28, 2021
Priority date	Aug 24, 2020
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

First claim

What is claimed is:

1. An integrated circuit comprising:
a plurality of logic cells in a first row extending in a first direction, the plurality of logic cells including different types of active areas extending in the first direction;
a filler cell in a second row extending in the first direction, the second row being adjacent to the first row in a second direction with a height thereof being different from a height of the first row, the second direction being orthogonal to the first direction;
a first routing wiring line in the second row, the first routing wiring line configured to connect a first logic cell and a second logic cell among the plurality of logic cells, the first logic cell and the second logic cell being spaced apart from each other by a first distance; and
a second routing wiring line in the second row, the second routing wiring line configured to connect a third logic cell and a fourth logic cell among the plurality of logic cells.

2. The integrated circuit of claim 1 , further comprising:
a plurality of power lines configured to provide supply voltages to the plurality of logic cells, wherein
the plurality of logic cells are between a set of the plurality of power lines configured to provide different ones of the supply voltages, and
the first routing wiring line is between a set of the plurality of power lines configured to provide a same one of the supply voltages.

3. The integrated circuit of claim 2 , wherein the filler cell is in a single type area on a substrate.

4. The integrated circuit of claim 3 , wherein
the first routing wiring line is between power lines providing a positive supply voltage, and
the filler cell is in a p-type area on the substrate.

5. The integrated circuit of claim 3 , wherein
the first routing wiring line is between power lines providing a negative supply voltage, and
the filler cell is in an n-type area on the substrate.

6. The integrated circuit of claim 1
wherein the third logic cell and the fourth logic cell are spaced apart from each other by a second distance, the second distance being less than the first distance, and
wherein a width of the first routing wiring line is greater than a width of the second routing wiring line.

7. The integrated circuit of claim 1 , wherein
the first row includes conductive wiring lines in a first wiring layer, the conductive wiring lines being at a first pitch, and
the second row includes routing wiring lines in the first wiring layer, the routing wiring lines being at a second pitch different from the first pitch.

8. An integrated circuit comprising:
a plurality of logic cells in a first row extending in a first direction, the plurality of logic cells having a first height in a second direction orthogonal to the first direction;
a plurality of decap cells in a second row extending in the first direction, the plurality of decap cells having a second height in the second direction and formed in a single type area on a substrate, the second height being less than the first height; and
a first routing wiring line in the second row, the first routing wiring line configured to connect a first logic cell and a second logic cell among the plurality of logic cells, the first logic cell and the second logic cell being spaced apart from each other by a first distance.

9. The integrated circuit of claim 8 , further comprising:
a plurality of power lines configured to provide supply voltages to the plurality of logic cells, wherein
the plurality of logic cells are between first power lines configured to provide different ones of the supply voltages, and
the plurality of decap cells are between second power lines configured to provide a same one of the supply voltages.

10. The integrated circuit of claim 9 , wherein each of the plurality of decap cells comprises:
a gate electrode extending in the second direction; and
an active pattern extending in the first direction such that the active pattern forms a transistor with the gate electrode and includes a source area and a drain area of the transistor, wherein
the gate electrode, the source area, and the drain area are connected to at least one of the second power lines.

11. The integrated circuit of claim 9 , wherein each of the plurality of decap cells comprises:
a gate electrode extending in the second direction; and
an active pattern extending in the first direction such that the active pattern forms a transistor with the gate electrode and includes a source area and a drain area of the transistor, wherein
at least one of the gate electrode, the source area, and the drain area is floated such that the at least one of the gate electrode, the source area, and the drain area is not connected to the first power lines or the second power lines.

12. The integrated circuit of claim 8 , further comprising:
a second routing wiring line in the second row, the second routing wiring line configured to connect a third logic cell and a fourth logic cell among the plurality of logic cells,
wherein the third logic cell and the fourth logic cell are spaced apart from each other by a second distance, the second distance being less than the first distance, and
wherein a width of the first routing wiring line is greater than a width of the second routing wiring line.

13. A method of designing an integrated circuit, the method comprising:
arranging a plurality of logic cells in a first row extending in a first direction;
arranging a plurality of filler cells in a second row extending in the first direction, the second row being adjacent to the first row in a second direction with a height thereof being less than a height of the first row, the second direction being orthogonal to the first direction;
adding a first routing wiring line to the second row such that the first routing wiring line is configured to connect a first logic cell and a second logic cell among the plurality of logic cells; and
adding a second routing wiring line to the second row such that the second routing wiring line is configured to connect a third logic cell and a fourth logic cell among the plurality of logic cells.

14. The method of claim 13 , wherein
the arranging the plurality of logic cells includes generating conductive wiring lines in a first wiring layer such that the conductive wiring lines are at a first pitch,
the adding the first routing wiring line includes generating the first routing wiring line in the first wiring layer such that the first routing wiring line is at a second pitch different from the first pitch.

15. The method of claim 14 , wherein the adding of the first routing wiring line comprises:
determining a width of the first routing wiring line in the second direction based on a length of the first routing wiring line in the first direction; and
arranging the first routing wiring line having the width determined based on the length thereof.

16. The method of claim 14 , wherein the generating the first routing wiring line comprises generating the first routing wiring line such that a width in the second direction increases as a length thereof in the first direction increases.

17. The method of claim 13 , further comprising:
generating a first set of power lines on an upper end boundary and a lower end boundary of the first row, respectively, the first set of power lines configured to provide different supply voltages to the plurality of logic cells; and
generating a second set of power lines on an upper end boundary and a lower end boundary of the second row, respectively, the second set of power lines co

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lim Seungman
• Jung Hakchul
• Baek Sanghoon
• Seo Jaewoo
• YU Jisu
• You Hyeongyu

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/981

  Power supply lines · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title