Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-12147137-B2
Application number	US-202318380203-A
Country	US
Kind code	B2
Filing date	Oct 16, 2023
Priority date	Sep 7, 2020
Publication date	Nov 19, 2024
Grant date	Nov 19, 2024

Abstract

An array substrate includes a base substrate, pixel electrodes and common electrodes, first scan lines, second scan lines and data lines. The pixel electrode has first electrode strips disposed at intervals in a row direction. The common electrodes and the pixel electrodes are disposed on the same layer, and the common electrodes have second electrode strips disposed at intervals. The second electrode strips and the first electrode strips are alternatively arranged. The first scan line is located between two adjacent rows of pixel electrodes. The second scan line is located between two adjacent columns of pixel electrodes and is electrically connected to the first scan line, and the second scan line has a scan signal input terminal. The data line has a data signal input terminal. An orthographic projection of the data line on the base substrate intersects with a central region of the pixel electrode on the base substrate.

First claim

What is claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of pixel electrodes, arranged in a form of array on the base substrate in a row direction and a column direction, wherein each of the pixel electrodes has a plurality of first electrode strips disposed at intervals in the row direction, and a first conductive connection portion located on a same side of the plurality of first electrode strips and connected to the plurality of first electrode strips; and each of the pixel electrodes is comb-shaped as a whole;
a plurality of common electrodes, disposed on a same layer as the pixel electrodes, wherein each of the common electrodes has a plurality of second electrode strips disposed at intervals in the row direction, and a second conductive connection portion located on a same side of the plurality of second electrode strips and connected to the plurality of second electrode strips; each of the common electrodes is comb-shaped as a whole; and the second electrode strips and the first electrode strips are alternatively arranged in the row direction;
a plurality of rows of first scan lines, formed between the base substrate and the pixel electrodes, wherein each row of the first scan lines is located between two adjacent rows of the pixel electrodes;
a plurality of columns of second scan lines, formed between the base substrate and the pixel electrodes, wherein each column of the second scan lines is located between two adjacent columns of the pixel electrodes and is electrically connected to the corresponding first scan line through a via hole structure, and a second scan line has a scan signal input terminal; and
a plurality of columns of data lines, formed between the base substrate and the pixel electrodes, wherein each column of the data lines has a data signal input terminal, a data line is provided with respect to a center of a pixel electrode in the row direction, and a size of the data line in the row direction is small than a size of a second electrode strip located above the data line in the row direction;
wherein, the array substrate further comprises first metal lines and second metal lines, a first metal line and a second metal line are located close to at least one of the second scan line or the data line in the row direction.

2. The array substrate according to claim 1 , wherein orthographic projections of the first metal line and the second metal line on the base substrate are located within an orthographic projection of the second electrode strip on the base substrate.

3. The array substrate according to claim 1 , wherein distances from the two sides of the data line in the row direction to a center of the pixel electrode in the row direction are equal to each other.

4. The array substrate according to claim 3 , wherein the two sides of the data line in the row direction are located on within both sides of one of the second electrode strips in the row direction.

5. The array substrate according to claim 4 , wherein the data lines and the second scan lines are provided on a same layer.

6. The array substrate according to claim 5 , wherein a number of the common electrodes is less than a number of the pixel electrodes in each row.

7. The array substrate according to claim 6 , wherein both sides of the second scan line in the row direction are located within two sides of one of the second electrode strips in the row direction.

8. The array substrate according to claim 6 , further comprising:
a plurality of rows of first common signal lines, wherein the first common signal lines and the first scan lines are disposed on a same layer, and each row of the first common signal lines is located between two adjacent rows of the pixel electrodes,
wherein one row of the first common signal lines and one row of the first scan lines are disposed between every two adjacent rows of the pixel electrodes, and each of the first common signal lines is electrically connected to the corresponding common electrode through a via hole structure.

9. The array substrate according to claim 8 , further comprising:
one or more columns of second common signal lines, wherein the second common signal lines and the second scan lines are disposed on a same layer, each column of the second common signal lines is located between two adjacent columns of the pixel electrodes and is electrically connected to each row of the first common signal lines through a via hole structure, and both sides of the second common signal line in the row direction are located within both sides of one of the second electrode strips in the row direction,
wherein a second common signal line has a common signal input terminal.

10. The array substrate according to claim 9 , wherein a column of the second scan lines is provided between two adjacent columns of the pixel electrodes of one portion of the pixel electrodes, and a column of the second common signal lines is provided between two adjacent columns of the pixel electrodes of another portion of the pixel electrodes.

11. The array substrate according to claim 9 ,
wherein a first metal line and a second metal line are located close to the second common signal line in the row direction.

12. The array substrate according to claim 9 , wherein the second electrode strip of the common electrode corresponding to the data line, the second scan line or the second common signal line has a size in the row direction larger than that of the other second electrode strips in the row direction.

13. The array substrate according to claim 9 , wherein the scan signal input terminal of the second scan line, the common signal input terminal of the second common signal line and the data signal input terminal of the data line are located on a same side of the base substrate.

14. The array substrate according to claim 1 , wherein each row of the first scan lines is electrically connected to two or more columns of the second scan lines.

15. The array substrate according to claim 5 , further comprising: a plurality of drive transistors, arranged in a form of array on the base substrate in the row direction and the column direction, wherein each of the drive transistors corresponds to one of the pixel electrodes,
wherein the drive transistor comprises a gate electrode disposed on a same layer as the first scan line, an active layer located on a side of the gate electrode distal to the base substrate, and a source-drain electrode disposed on a same layer as the data line,
a gate insulating layer is formed between the gate electrode and the active layer, wherein the gate insulating layer covers the gate electrode and the first scan line, a passivation layer is formed between the source-drain electrode and the pixel electrode, and the passivation layer covers the source-drain electrode, the data line and the second scan line, and
the first scan line is electrically connected to the gate electrode, the data line is electrically connected to a source electrode in the source-drain electrode, and the pixel electrode is electrically connected to a drain electrode in the source-drain electrode via a via hole structure penetrating the passivation layer.

16. The array substrate according to claim 15 , further comprising: an organic insulating layer, formed between the passivation layer and the pixel electrode, wherein the pixel electrode is electrically connected to the drain electrode via a via hole structure penetrating the organic insulating layer and the passivation layer.

17. The array substrate according to claim 16 , further comprising: a color filter layer, formed

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Zhou Maoxiu
• Liao Yanping
• Miao Yingmeng
• Zhang Yuntian
• Guo Lei
• Dai Ke
• Yang Haipeng
• Sun Zhihua
• Shao Xibin
• Wang Zhangtao

Classifications

• G02F1/1368

  in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} · CPC title

• G02F1/136227

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/134363

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title