Array substrate and display device

Patent metadata

Field	Value
Publication number	US-2016147123-A1
Application number	US-201414435923-A
Country	US
Kind code	A1
Filing date	Sep 18, 2014
Priority date	Jun 13, 2014
Publication date	May 26, 2016
Grant date	—

Abstract

An array substrate and a display device are provided. A common electrode line with the same extending direction as a gate line is disposed at one end near a thin film transistor, and forms a storage capacitor with a drain electrode of the thin film transistor. As compared with the case in the prior art that a common electrode line and a thin film transistor in an array substrate are disposed at both ends of a pixel, respectively, and it is necessary to separately provide a storage capacitance electrode useful for forming a storage capacitor with the common electrode line, the pixel region occupied by the thin film transistor and the common electrode line can be effectively decreased. Thus, the aperture ratio is increased, and the display brightness of an IPS liquid crystal display device is enhanced.

First claim

1 . An array substrate, comprising a gate line, a data line and a common electrode line, a region defined by adjacent gate lines and adjacent data lines is a pixel, which includes a thin film transistor lying in the vicinity of an intersection of the gate line and the data line and electrically connected to the gate line and the data line, respectively, a plurality of pixel electrodes, a pixel electrode connecting section connected to the plurality of the pixel electrodes, a plurality of common electrodes disposed in a same layer as and arranged intervally with the pixel electrodes, and a common electrode connecting section connected to the plurality of the common electrodes, wherein,
the common electrode line has a same extending direction as the gate line, and is located at one end of the pixel near the thin film transistor, and forms a storage capacitor with a drain electrode of the thin film transistor; the pixel further includes a wire for electrically connecting the common electrode line and each of the common electrodes.

2 . The array substrate according to claim 1 , wherein, the wire is electrically connected to the common electrodes through the common electrode connecting section.

3 . The array substrate according to claim 1 , wherein, an orthographic projection of the wire on the array substrate lies within a region where the data line is located.

4 . The array substrate according to claim 1 , wherein, the wire has a same extending direction as the data line, and an orthographic projection of the wire on the array substrate lies between the data line and the pixel electrode adjacent to it.

5 . The array substrate according to claim 2 , wherein, an orthographic projection of the wire on the array substrate partially lies within a region where the data line is located.

6 . The array substrate according to claim 1 , wherein, the wire is provided in single, and is located at one end of the pixel near the thin film transistor.

7 . The array substrate according to claim 6 , wherein, the pixel further includes a shielding electrode line located at one end far away from the thin film transistor;
the shielding electrode line has a same extending direction as the data line; an orthographic projection of the shielding electrode line on the array substrate lies between a data line and the pixel electrode adjacent to it, or the orthographic projection of the shielding electrode line on the array substrate lies within the region where the data line is located, or the orthographic projection of the shielding electrode line on the array substrate partially lies within the region where the data line is located.

8 . The array substrate according to claim 7 , wherein, one end of the shielding electrode line is electrically connected to the common electrode line; or,
the other end of the shielding electrode line is electrically connected to the common electrode connecting section; or, both ends of the shielding electrode line is arranged to be floated.

9 . The array substrate according to claim 8 , wherein, the shielding electrode line is disposed in a same layer as the wire and the common electrode line.

10 . The array substrate according to claim 1 , wherein, the pixel electrodes and the common electrodes are strip-like electrodes extending in a direction parallel to the data line, and the plurality of pixel electrodes and the plurality of common electrodes are distributed alternately.

11 . The array substrate according to claim 10 , wherein, the pixel electrode connecting section extends along a direction parallel to the gate line, and ends of the plurality of pixel electrodes near the thin film transistor are connected together; the common electrode connecting section extends along a direction parallel to the gate line, and ends of the plurality of common electrodes far away from the thin film transistor are connected together.

12 . A display device, comprising the array substrate according to claim 1 .

13 . The array substrate according to claim 2 , wherein, an orthographic projection of the wire on the array substrate lies within a region where the data line is located.

14 . The array substrate according to claim 2 , wherein, the wire has a same extending direction as the data line, and an orthographic projection of the wire on the array substrate lies between the data line and the pixel electrode adjacent to it.

15 . The display device according to claim 12 , wherein, the wire is electrically connected to the common electrodes through the common electrode connecting section.

16 . The display device according to claim 12 , wherein, an orthographic projection of the wire on the array substrate lies within a region where the data line is located.

17 . The display device according to claim 12 , wherein, the wire has a same extending direction as the data line, and an orthographic projection of the wire on the array substrate lies between the data line and the pixel electrode adjacent to it.

18 . The display device according to claim 15 , wherein, an orthographic projection of the wire on the array substrate partially lies within a region where the data line is located.

19 . The display device according to claim 12 , wherein, the wire is provided in single, and is located at one end of the pixel near the thin film transistor.

20 . The display device according to claim 19 , wherein, the pixel further includes a shielding electrode line located at one end far away from the thin film transistor;
the shielding electrode line has a same extending direction as the data line; an orthographic projection of the shielding electrode line on the array substrate lies between a data line and the pixel electrode adjacent to it, or the orthographic projection of the shielding electrode line on the array substrate lies within the region where the data line is located, or the orthographic projection of the shielding electrode line on the array substrate partially lies within the region where the data line is located.

Assignees

• Boe Technology Group Co Ltd

Inventors

• Cheng Hongfei
• Qiao Yong
• Xian Jianbo
• Li Wenbo
• Li Pan

Classifications

• H10D86/481

  integrated with passive devices, e.g. auxiliary capacitors · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• G02F1/134363 Primary

  for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS] · CPC title

• G02F2001/136218

  Physics · mapped topic