Back end of line embedded RRAM structure with low forming voltage

Patent metadata

Field	Value
Publication number	US-12144271-B2
Application number	US-202117444841-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Aug 11, 2021
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

A semiconductor structure may include a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip. The resistive random access memory may include a first electrode and a second electrode separated by a dielectric film. A portion of the dielectric film directly above the first electrode may be crystalline. The semiconductor structure may include a stud below and in electrical contact with the first electrode and the lower metal interconnect and a dielectric layer between the upper metal interconnect and the lower metal interconnect. The dielectric layer may separate the upper metal interconnect from the lower metal interconnect. The crystalline portion of the dielectric film may include grain boundaries that extend through an entire thickness of the dielectric film. The crystalline portion of the dielectric film may include grains.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip, the resistive random access memory includes a first electrode and a second electrode separated by a dielectric film, wherein a portion of the dielectric film directly above the first electrode is crystalline;
a stud below and in electrical contact with the first electrode and the lower metal interconnect; and
a dielectric layer between the upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect.

2. The semiconductor structure of claim 1 , wherein the crystalline portion of the dielectric film includes grain boundaries that extend through an entire thickness of the dielectric film.

3. The semiconductor structure of claim 1 , wherein the crystalline portion of the dielectric film includes grains, wherein an average grain size is larger than a thickness of the dielectric film.

4. The semiconductor structure of claim 1 , wherein a thickness of the portion of the dielectric film that is crystalline is less than 5 nm.

5. The semiconductor structure of claim 1 , wherein the dielectric film is made of hafnium oxide.

6. The semiconductor structure of claim 1 , wherein the dielectric layer between the upper metal interconnect and the lower metal interconnect is made of silicon oxide.

7. The semiconductor structure of claim 1 , wherein the stud bridges a distance from the first electrode of the resistive random access memory to the lower metal interconnect.

8. A semiconductor structure comprising:
a resistive random access memory device embedded between an upper metal interconnect and a lower metal interconnect in a backend structure of a chip, the resistive random access memory includes a first electrode and a second electrode separated by a dielectric film, wherein the second electrode is below and in electrical contact with the upper metal interconnect, wherein a portion of the dielectric film directly above the first electrode is crystalline;
a stud below and in electrical contact with the first electrode and the lower metal interconnect, wherein the stud is made of a refractory metal; and
a dielectric layer between the upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect.

9. The semiconductor structure of claim 8 , wherein the crystalline portion of the dielectric film includes grain boundaries that extend through an entire thickness of the dielectric film.

10. The semiconductor structure of claim 8 , wherein the crystalline portion of the dielectric film includes grains, wherein an average grain size is larger than a thickness of the dielectric film.

11. The semiconductor structure of claim 8 , wherein the dielectric film is made of hafnium oxide.

12. The semiconductor structure of claim 8 , wherein the dielectric layer between the upper metal interconnect and the lower metal interconnect is made of silicon oxide.

13. The semiconductor structure of claim 8 , wherein the stud bridges a distance from the first electrode of the resistive random access memory to the lower metal interconnect.

14. A method comprising:
forming a stud below and in electrical contact with a first electrode and a lower metal interconnect;
depositing a dielectric layer between an upper metal interconnect and the lower metal interconnect, the dielectric layer separates the upper metal interconnect from the lower metal interconnect;
forming a resistive random access memory device embedded between the upper metal interconnect and the lower metal interconnect in a backend structure of a chip, the resistive random access memory includes the first electrode and a second electrode separated by a dielectric film; and
laser annealing the dielectric film to crystalize a portion of the dielectric film above the first electrode.

15. The method of claim 14 , wherein the crystalline portion of the dielectric film includes grain boundaries that extend through an entire thickness of the dielectric film.

16. The method of claim 14 , wherein the crystalline portion of the dielectric film includes grains, wherein an average grain size is larger than a thickness of the dielectric film.

17. The method of claim 14 , wherein the dielectric film is made of hafnium oxide.

18. The method of claim 14 , wherein the dielectric layer between the upper metal interconnect and the lower metal interconnect is made of silicon oxide.

19. The method of claim 14 , wherein the stud bridges a distance from the first electrode of the resistive random access memory to the lower metal interconnect.

20. The method of claim 14 , wherein the laser annealing includes a plurality of short duration laser anneal pulses.

Assignees

• IBM

Inventors

• Gluschenkov Oleg
• Reznicek Alexander
• Kim Youngseok
• Ok Injo
• Seo Soon-Cheon

Classifications

• H10B63/30 Primary

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10N70/841

  Electrodes · CPC title

• H10N70/235

  between different crystalline phases, e.g. cubic and hexagonal · CPC title

• H10N70/066

  by filling of openings, e.g. damascene method · CPC title

• H10N70/063

  by etching of pre-deposited switching material layers, e.g. lithography · CPC title