Vertical memory cell for high-density memory

Patent metadata

Field	Value
Publication number	US-10333064-B2
Application number	US-201113086321-A
Country	US
Kind code	B2
Filing date	Apr 13, 2011
Priority date	Apr 13, 2011
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.

First claim

What is claimed is:

1. A memory device, comprising:
a vertical resistive random access memory (RRAM) cell comprising:
a first electrode;
a second electrode; and
an active material comprising an inner circumference having an entirely circular shape and an outer circumference having an entirely circular shape circumscribing the inner circumference, wherein the active material is disposed between the first electrode and the second electrode, wherein the active material directly contacts the first electrode and the second electrode respectively, wherein the second electrode contacts the entire inner circumference of the active material in directly contacting the active material, wherein the active material has variable resistive properties and comprises a columnar grain structure defining a plurality of grain boundaries oriented generally perpendicular to the first electrode and generally perpendicular to the second electrode, wherein the plurality of grain boundaries are oriented generally parallel to a plane of a substrate upon which the RRAM cell is formed.

2. The memory device of claim 1 , wherein the application of an activation voltage to the active material creates an electrical field between the first electrode and the second electrode, and wherein the plurality of grain boundaries are oriented generally parallel to the electrical field.

3. The memory device of claim 1 , wherein the application of an activation voltage causes the active material to transition from a high resistive state to a low resistive state.

4. The memory device of claim 3 , wherein when the active material is in the low resistive state, a conductive pathway is formed between the first electrode and the second electrode and generally along one of the plurality of grain boundaries.

5. The memory device of claim 4 , wherein the conductive pathway has a tortuosity of approximately unity.

6. The memory device of claim 1 , wherein the active material comprises a polycrystalline material.

7. The memory device of claim 1 , wherein the active material comprises at least one of a chalcogenide, a transition-metal oxide, and a complex metal oxide.

8. A memory device, comprising:
a vertical resistive random access memory (RRAM) cell comprising:
a first electrode;
a second electrode; and
an active material comprising an inner circumference having an entirely circular shape and an outer circumference having an entirely circular shape circumscribing the inner circumference, wherein the active material is disposed between the first electrode and the second electrode, wherein one end of the active material interfaces with a surface of the first electrode, wherein a second end of the active material, opposite to the first end of the active material, interfaces with a surface of the second electrode, wherein the second electrode contacts the entire inner circumference of the active material in interfacing with the second end of the active material, wherein a particular dimension of the first electrode is selected to ensure the creation of at least one grain boundary oriented generally perpendicular to the first electrode and generally perpendicular to the second electrode within the active material that is suitable for the formation of a conductive path between the first electrode and the second electrode when the RRAM cell is in an on state, wherein the at least one grain boundary is oriented generally parallel to a plane of a substrate upon which the RRAM cell is formed.

9. The memory device of claim 8 , wherein the first electrode comprises a word line coupled to the RRAM cell, and wherein the particular dimension comprises a height of the word line.

10. The memory device of claim 9 , wherein the height of the word line is selected as being between approximately 5 nanometers to approximately 100 nanometers.

11. The memory device of claim 8 , wherein the first electrode comprises a word line coupled to the RRAM cell, wherein the surface of the word line that interfaces with the active material has one of a convex or a concave shape, and wherein the particular dimension comprises a distance of a curvature of the convex or the concave surface.

12. The memory device of claim 11 , comprising a first dielectric layer disposed below the word line and a second dielectric layer disposed above the word line; wherein, if the interfacing surface of the word line is convex, the convex interfacing surface is formed by applying a semi-selective etchant that removes portions of the first and second dielectric layers at a faster rate than portions of the word line; and wherein, if the interfacing surface of the word line is concave, the concave interfacing surface is formed by applying a semi-selective etchant that removes portions of the word line at a faster rate than portions of the first and second dielectric layers.

13. The memory device of claim 8 , wherein varying the particular dimension does not increase an aerial footprint of the RRAM cell.

14. The memory device of claim 8 , wherein the RRAM cell comprises a nanoscopic dimension, and wherein the selected particular dimension of first electrode maintains apparent continuum behavior properties in the RRAM cell.

15. A multiple-tier three-dimensional memory device comprising:
a first tier of word lines;
a second tier of word lines formed above the first tier of word lines;
a cavity extending through at least one word line from the first tier and at least one word line from the second tier, wherein the at least one word line from the first tier and the at least one word line from the second tier are in the same vertical plane such that a circumference of the cavity is completely surrounded by each of the at least one word line from the first tier and the at least one word line from the second tier; and
a vertical memory cell structure, wherein the vertical memory cell structure is at least partially disposed in the cavity, wherein the vertical memory cell structure comprises:
an active material disposed circumferentially within the cavity, wherein the active material comprises an inner circumference having an entirely circular shape and an outer circumference having an entirely circular shape circumscribing the inner circumference, wherein the active material comprises a variable resistive material switchable between a low resistive state and a high resistive state;
a conductive element disposed within the cavity, wherein the conductive element is configured to directly contact the entire inner circumference of the active material;
wherein a first resistive memory cell comprises the conductive element, the active material, and the word line from the first tier, and wherein a second resistive memory cell comprises the conductive element, the active material, and the word line from the second tier, wherein the second resistive memory cell is above the first resistive memory cell.

16. The multiple-tier three-dimensional memory device of claim 15 , wherein the cavity comprises a through-hole, a trench, or a slot.

17. The multiple-tier three-dimensional memory device of claim 16 , wherein if the cavity comprises a through-hole, the conductive element comprises a conductive via.

18. The multiple-tier three-dimensional memory array of claim 15 , wherein the plurality of vertical memory cell structures comprises a first vertical memory cell structure, a second vertical memory cell structure, and a third memory cell structure, wherein the first and second vertical memory cell structures are in a first common vertical plane and wherein the first and third vertical

Assignees

• Sills Scott E
• Sandhu Gurtej
• Micron Technology Inc

Inventors

• Sills Scott E
• Sandhu Gurtej

Classifications

• H01L45/143

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic

• H01L45/147

  Electricity · mapped topic

• H01L45/1226 Primary

  Electricity · mapped topic

• H01L45/142

  Electricity · mapped topic