Display substrate, pixel circuit, driving method and display apparatus

Patent metadata

Field	Value
Publication number	US-12142211-B2
Application number	US-202117795869-A
Country	US
Kind code	B2
Filing date	Sep 15, 2021
Priority date	Sep 15, 2021
Publication date	Nov 12, 2024
Grant date	Nov 12, 2024

Abstract

A display substrate, a pixel circuit, a driving method and a display device are provided. The display substrate includes a substrate and a plurality of repeating units arranged in an array on one side of the substrate, each repeating unit includes at least two light emitting elements and at least two pixel circuits, each pixel circuit includes a first transistor, a second transistor and a third transistor, and the third transistor is configured to drive the light emitting element to emit light; each repeating unit further includes a first region, a second region and a third region arranged continuously in the first direction, the first region includes at least two of the first transistors, the third region including at least two of the third transistors, and the type of the first transistor and the type of the third transistor are different.

First claim

The invention claimed is:

1. A pixel circuit, comprising: a first transistor, a second transistor, and a third transistor, wherein a control electrode of the first transistor is connected to a scan signal line, a first electrode of the first transistor is connected to a data signal line, and a second electrode of the first transistor is connected to a first node; a control electrode of the second transistor is connected to a reference signal line, a first electrode of the second transistor is connected to a second node, and a second electrode of the second transistor is connected to a first electrode of a light emitting element; a control electrode of the third transistor is connected to the first node, a first electrode of the third transistor is connected to a first power supply line, and a second electrode of the third transistor is connected to the second node; and
wherein the first transistor is configured to supply a signal of the data signal line to the third transistor under control of a signal of the scan signal line; the second transistor is configured to supply a signal of the second node to the first electrode of the light emitting element under control of a signal of the reference signal line; and the third transistor is configured to supply a signal of the first power supply line to the second node under control of the signal of the data signal line,
the pixel circuit further comprising a first test circuit connected to a test enable signal line, the third transistor, a third power supply line and a fourth power supply line, and is configured to, under control of a signal of the test enable signal line, switch a connection state of the third transistor from a first connection state to a second connection state, supply a fixed voltage output by the fourth power supply line to the third transistor, and control the third transistor to be in a forward bias state; wherein, the first connection state is that a substrate terminal of the third transistor is connected to the third power supply line, and the second connection state is that the substrate terminal of the third transistor is connected to the fourth power supply line; and,
the second transistor is configured to, under control of a signal of the reference signal line, supply a fixed voltage output by the fourth power supply line to the first electrode of the light emitting element.

2. The pixel circuit of claim 1 , further comprising a storage capacitor, wherein a first electrode plate of the storage capacitor is connected to the first node and a second plate of the storage capacitor is connected to a second power supply line.

3. The pixel circuit of claim 1 , further comprising a fourth transistor, wherein a control electrode of the fourth transistor is connected to a discharge signal line, a first electrode of the fourth transistor is connected to the second node, and a second electrode of the fourth transistor is connected to an initial signal line; the fourth transistor is configured to supply a signal of the initial signal line to the second node under control of a signal of the discharge signal line.

4. The pixel circuit of claim 3 , wherein the second transistor is further configured to be in a reverse biased state in a case that a short circuit occurs between the first electrode of the light emitting element and a second electrode of the light emitting element.

5. The pixel circuit of claim 1 , further comprising a gate voltage control sub-circuit connected to the reference signal line and configured to supply a variable voltage to the control electrode of the second transistor.

6. The pixel circuit of claim 1 , wherein a substrate terminal of the third transistor is connected to a third power supply line; the pixel circuit further comprises: substrate voltage control sub-circuit connected to the third power supply line, and is configured to, in a case of being in a high-brightness mode, apply a first voltage to the substrate terminal of the third transistor, or, in a case of being in a low-brightness mode, apply a second voltage to the substrate terminal of the third transistor, wherein an absolute value of the first voltage is greater than an absolute value of the second voltage, a brightness parameter of the high-brightness mode is higher than a preset brightness threshold, and a brightness parameter of the low-brightness mode is not higher than the preset brightness threshold.

7. The pixel circuit of claim 1 , wherein the first test circuit comprises a first switch device and a second switch device; a first terminal of the first switch device is connected to the substrate terminal of the third transistor, and a second terminal of the first switch device is connected to the third power supply line; a first terminal of the second switch device is connected to the substrate terminal of the third transistor, and a second terminal of the second switch device is connected to the fourth power supply line;
the first test circuit is configured to, under control of the signal of the test enable signal line, switch the first switch device from an on state to an off state and switch the second switch device from an off state to an on state.

8. The pixel circuit of claim 3 , further comprising a second test circuit;
wherein,
the control electrode of the fourth transistor is connected to a monochrome enable signal line, and the fourth transistor is further configured to, under control of a signal of the monochrome enable signal line, control a light emitting element connected to the monochrome enable signal line to emit a monochrome light ray corresponding to the signal of the monochrome enable signal line; the monochrome enable signal line comprises a first enable signal line connected to a light emitting element emitting a first color, a second enable signal line connected to a light emitting element emitting a second color, and a third enable signal line connected to a light emitting element emitting a third color;
the second test circuit is connected to the second electrode of the fourth transistor, a switch signal line, a monochrome test signal line, and a fourth power supply line, and is configured to, under control of a signal of the switch signal line, switch a connection state of the fourth transistor between a third connection state and a fourth connection state, and to supply a signal of the monochrome test signal line or a signal of the fourth power supply line to the fourth transistor; wherein, the third connection state is that the second electrode of the fourth transistor is connected to the monochrome test signal line, and the fourth connection state is that the second electrode of the fourth transistor is connected to the fourth power supply line.

9. The pixel circuit of claim 8 , wherein the second test circuit comprises a third switch device and a fourth switch device; a first terminal of the third switch device is connected to the second electrode of the fourth transistor, and a second terminal of the third switch device is connected to the monochrome test signal line; a first terminal of the fourth switch device is connected to the second electrode of the fourth transistor, and a second terminal of the fourth switch device is connected to the fourth power supply line.

10. A driving method, applied to the pixel circuit of claim 1 , the driving method comprises a data writing stage and an emitting stage, wherein
in the data writing stage, supplying a signal of the data signal line to the control electrode of the third transistor under control of the signal of the scan signal line;
in the emitting stage, turning the third transistor on under control of the signal of the data signal line, turning the second transistor on under control of the signal

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Junbo
• Li Dachao
• Yang Shengji
• Lu Pengcheng
• Huang Kuanta
• Zhu Zhijian
• Tian Yuanlan

Classifications

• G09G2330/08

  Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title