Multi-chip package

Patent metadata

Field	Value
Publication number	US-12136608-B2
Application number	US-202318166931-A
Country	US
Kind code	B2
Filing date	Feb 9, 2023
Priority date	Jul 30, 2019
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A multi-chip package including a first integrated circuit and a second integrated circuit. The first integrated circuit includes a first side having a first conductive layer, a second side having a second conductive layer, and an edge, the first conductive layer coupled to the second conductive layer at a location adjacent to the edge. The second integrated circuit is coupled to the second conductive layer of the first integrated circuit.

First claim

The invention claimed is:

1. A method, comprising:
forming a plurality of first dielectric layers and a plurality of first conductive layers on a first surface of a semiconductor substrate;
forming a first sidewall of the semiconductor substrate by forming a first recess extending through the semiconductor substrate from a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate, the forming the first recess including forming the first recess to extend to the first surface of the semiconductor substrate exposing a contact pad of the plurality of first conductive layers within the plurality of first dielectric layers;
forming a second sidewall and a recessed surface of the semiconductor substrate by forming a second recess extending into the second surface of the semiconductor substrate, the forming the second recess including terminating the second recess before reaching the first surface of the semiconductor substrate;
forming a second dielectric layer on the recessed surface, the second sidewall, and the first sidewall of the semiconductor substrate;
forming a second conductive layer on the second dielectric layer and overlapping the recessed surface, the second sidewall, and the first sidewall; and
coupling a die to the second conductive layer and overlapping the die with the semiconductor substrate.

2. The method of claim 1 , wherein:
the forming the first sidewall further includes forming the first sidewall having a first incline with a first slope; and
the forming the second sidewall further includes forming the second sidewall having a second incline with a second slope.

3. The method of claim 2 , wherein the first sidewall having the first incline with the first slope is at an angle greater than 90-degrees relative to a surface of the plurality of dielectric layers on the semiconductor substrate.

4. The method of claim 2 , wherein the second sidewall having the second incline with the second slope is at an angle greater than 90-degrees relative to a surface of the plurality of dielectric layers on the semiconductor substrate.

5. The method of claim 1 , wherein the forming a second conductive layer further includes forming the second conductive layer on the contact pad of the plurality of first conductive layers.

6. The method of claim 1 , wherein the coupling the die to the second conductive layer further includes forming at least one solder ball between the die and the second conductive layer coupling the die to the second conductive layer.

7. The method of claim 6 , further comprising forming a third dielectric layer between the die and the second dielectric layer and covering the at least one solder ball between the die and the second conductive layer.

8. The method of claim 1 , wherein the forming the second dielectric layer further includes forming the second dielectric layer on a surface of the plurality of dielectric layers on the semiconductor substrate.

9. The method of claim 1 , further comprising singulating the plurality of first dielectric layers, the second dielectric layer, and the second conductive layer.

10. The method of claim 1 , further comprising forming a molding compound covering the semiconductor substrate and the die.

11. The method of claim 10 , further comprising forming a semiconductor device by singulating the plurality of first dielectric layers, the second dielectric layer, the second conductive layer, and the molding compound.

12. The method of claim 11 , wherein the singulating the plurality of first dielectric layers, the second dielectric layer, the second conductive layer and the molding compound further includes forming a third sidewall of the semiconductor device along which respective sidewalls of the plurality of first dielectric layers, the second dielectric layer, the second conductive layer, and the molding compound are coplanar.

13. A method, comprising:
forming a plurality of first dielectric layers and a plurality of first conductive layers on a first surface of a semiconductor substrate;
forming a first sidewall of the semiconductor substrate by forming a recess extending through the semiconductor substrate from a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate, the forming the recess including forming the recess to extend to the first surface of the semiconductor substrate exposing a contact pad of the plurality of first conductive layers within the plurality of dielectric layers;
forming a second dielectric layer on the first sidewall of the semiconductor substrate and on the second surface of the semiconductor substrate;
forming a second conductive layer on the second dielectric layer and overlapping a second sidewall; and
coupling a die to the second conductive layer and overlapping the die with the semiconductor substrate.

14. The method of claim 13 , wherein the coupling the die to the second conductive layer further includes forming at least one solder ball coupling the die to the second conductive layer.

15. The method of claim 14 , further comprising forming a third dielectric layer between the die and the second conductive layer and covering the at least one solder ball.

16. The method of claim 14 , wherein the forming the second conductive layer further includes forming the second conductive layer on the contact pad of the plurality of first conductive layers within the plurality of first dielectric layers.

17. The method of claim 14 , further comprising forming a molding compound covering the die and the semiconductor substrate, and on a surface of the plurality of dielectric layers on the semiconductor substrate.

18. A method, comprising:
forming a plurality of first dielectric layers and a plurality of first conductive layers on a first surface of a semiconductor substrate;
forming an inclined sidewall of the semiconductor substrate by forming a first recess extending into a second surface of the semiconductor substrate opposite to the first surface of the semiconductor substrate, the forming the first recess including forming the first recess extending from the second surface to the first surface, exposing a surface of the plurality of dielectric layers on which the semiconductor substrate is on, and exposing a contact pad at the surface of the plurality of dielectric layers;
forming a second dielectric layer on the inclined sidewall of the semiconductor substrate, on the surface of the plurality of dielectric layers, and on the second surface of the semiconductor substrate;
forming a second conductive layer on the dielectric layer and on the contact pad of the plurality of first conductive layers; and
coupling a die to the second conductive layer and overlapping the second surface of the semiconductor substrate.

19. The method of claim 18 , further comprising, before the forming the second dielectric layer, recessing the second surface of the semiconductor substrate within the semiconductor substrate by forming a second recess extending into the semiconductor substrate towards the first surface of the semiconductor substrate and terminating the second recess before reaching the first surface of the semiconductor substrate.

20. The method of claim 18 , further comprising:
forming at least one solder ball coupling the die to the second conductive layer; and
forming a third dielectric layer between the die and the second conductive layer and covering the at least one solder ball.

Assignees

• St Microelectronics Pte Ltd

Inventors

• Chen Yong
• Gani David

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/20

  Configurations of stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title