Method of forming a chip package, method of forming a semiconductor arrangement, chip package, and semiconductor arrangement

Patent metadata

Field	Value
Publication number	US-12136583-B2
Application number	US-202117519805-A
Country	US
Kind code	B2
Filing date	Nov 5, 2021
Priority date	Nov 5, 2020
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A method of forming a chip package is provided. The method may include: arranging an elastic thermal interface material over a semiconductor chip, wherein the elastic thermal interface material may be configured to transfer heat from the chip to an outside; arranging a mold around the thermal interface material and at least partially around the semiconductor chip, thereby compressing the elastic thermal interface material with the mold; and filling the mold with a packaging material.

First claim

What is claimed is:

1. A chip package, comprising:
a semiconductor chip;
an elastic thermal interface material over the semiconductor chip, wherein the elastic thermal interface material is configured to transfer heat from the semiconductor chip to an outside;
a packaging material around the elastic thermal interface material and at least partially around the semiconductor chip; and
a gap between the elastic thermal interface material and the packaging material that is arranged directly above and extends along an upper surface of the semiconductor chip,
wherein the elastic thermal interface material extends above a surface level of the packaging material.

2. The chip package of claim 1 , wherein a height difference between the elastic thermal interface material and the surface of the packaging material is at least 20 μm.

3. The chip package of claim 1 , wherein the elastic thermal interface material forms a layer with a thickness of at least 20 μm.

4. The chip package of claim 1 , wherein the elastic thermal interface material is arranged in direct physical contact with the semiconductor chip.

5. The chip package of claim 1 , further comprising:
a clip mounted on the semiconductor chip,
wherein the elastic thermal interface material is arranged in direct physical contact with the clip.

6. The chip package of claim 1 , wherein the elastic thermal interface material has a Young's modulus of less than 10 GPa at least at a molding temperature of the packaging material.

7. The chip package of claim 1 , wherein the elastic thermal interface material comprises a silicone material, epoxy and/or acrylic.

8. A semiconductor arrangement, comprising:
the chip package of claim 1 ; and
a cooling structure attached to the elastic thermal interface material.

9. The semiconductor arrangement of claim 8 , wherein the cooling structure is configured to extend into the gap of the chip package.

Assignees

• Infineon Technologies Ag

Inventors

• Ng Chee Yang

Classifications

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/016

  using moulds · CPC title

• H10W40/778

  in encapsulations · CPC title

• H10W40/226

  characterised by projecting parts, e.g. fins to increase surface area (leadframes for cooling H10W70/461) · CPC title

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title