Avoiding use of a subarray of configurable units having a defect

Patent metadata

Field	Value
Publication number	US-12135971-B2
Application number	US-202318236584-A
Country	US
Kind code	B2
Filing date	Aug 22, 2023
Priority date	Jul 16, 2021
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A computing system includes an array of configurable units made up of sub-arrays of configurable units. Each sub-array has a first number of configurable compute units and a second number of configurable memory units with a first spatial arrangement. Each configurable unit includes a configuration data store. The system also includes a statically configurable bus system coupled to the configurable units and a tag indicating a sub-array of configurable units having a defect. A defect-aware configuration controller sends configuration data to the configuration data stores to implement a data processing operation using the array of configurable units by generating static route control signals for the statically configurable bus system, based on the tag and without support of a host processor, to send a portion of the configuration data targeted to the sub-array having the defect to a configuration data store of an alternative sub-array of configurable units in the array.

First claim

The invention claimed is:

1. A computing system comprising:
an array of configurable units comprising sub-arrays of configurable units, each sub-array in the sub-arrays of configurable units consisting of a first number of configurable compute units and a second number of configurable memory units having a first spatial arrangement, configurable units in the array of configurable units including a respective configuration data store to configure the respective configurable unit;
a statically configurable bus system coupled to the configurable units in the array of configurable units;
a tag indicating a sub-array of configurable units in the array of configurable units having a defect; and
a defect-aware configuration controller to send configuration data to the configuration data stores to implement a data processing operation using the array of configurable units by generating static route control signals for the statically configurable bus system, based on the tag and without support of a host processor, to send a portion of the configuration data targeted to the sub-array having the defect to a configuration data store of an alternative sub-array of configurable units in the array.

2. The computing system of claim 1 , wherein the array of configurable units, the statically configurable bus system, a parameter store to hold the tag, the defect-aware configuration controller, and a port to connect to an external memory are all included on a single integrated circuit die.

3. The computing system of claim 1 , wherein the array of configurable units, the statically configurable bus system, a parameter store to hold the tag, and the defect-aware configuration controller are all included in a multi-chip module.

4. The computing system of claim 1 , the statically configurable bus system including an array of switches interleaved with the array of configurable units, and repair control signals applied to switches in the array of switches by the defect-aware configuration controller indicating relative positions of the switches to the sub-array having the defect.

5. The computing system of claim 4 , the switches in the array of switches respectively including:
first input ports and first output ports connecting the respective switch to other switches in the array of switches;
second input ports and second output ports connecting the respective switch to one or more configurable units in the array of configurable units; and
routing logic to forward a data packet received on an input port of the first input ports or the second input ports on the respective switch to an output port of the first output ports or the second output ports on the respective switch selected, at least in part, based on one or more of the repair control signals.

6. The computing system of claim 5 , wherein the data packet includes the portion of the configuration data targeted to the sub-array having the defect.

7. The computing system of claim 5 , wherein the data packet includes data sent by a first configurable unit in the array of configurable units to a second configurable unit in the array of configurable units as a part of the data processing operation.

8. The computing system of claim 1 , including:
a control signal path arranged in a daisy chain through the configurable units in the array of configurable units; and
logic circuits to configure the control signal path to bypass the sub-array having the defect based on the tag.

9. The computing system of claim 1 , further comprising a memory to store the configuration data to be read by the defect-aware configuration controller.

10. A method for avoiding use a sub-array of configurable units with a defect in a computing system having an array of configurable units, comprising a plurality of sub-arrays of configurable units including the sub-array of configurable units with the defect coupled to a statically configurable bus system, the method comprising:
reading a tag from a parameter store in the computing system indicating a sub-array of configurable units in the array of configurable units having the defect; and
using a defect-aware configuration controller coupled to the statically configurable bus system to place configuration data that implements a data processing operation into configuration data stores of the configurable units of the array of configurable units by generating static route control signals for the statically configurable bus system, based on the tag and without support of a host processor, to send a portion of the configuration data targeted to the sub-array having the defect to a configuration data store of an alternative sub-array of the plurality of sub-arrays of configurable units.

11. The method of claim 10 , further comprising generating and applying repair control signals to switches of the statically configurable bus system indicating relative positions of the switches to the sub-array having the defect.

12. The method of claim 11 , including routing, responsive to the repair control signals, a data packet received on an input port on a switch of the switches of the statically configurable bus system to an output port on the switch.

13. The method of claim 12 , wherein the data packet includes the portion of the configuration data targeted to the sub-array having the defect.

14. The method of claim 12 , wherein the data packet includes data sent by a first configurable unit in the array of configurable units to a second configurable unit in the array of configurable units as a part of the data processing operation.

15. The method of claim 10 , including executing a configuration load procedure using the statically configurable bus system for the placement of the configuration data in the processors.

16. The method of claim 10 , further comprising performing the data processing operation using a subset of the plurality of sub-arrays of configurable units that excludes the sub-array having the defect.

Assignees

• Sambanova Systems Inc

Inventors

• Grohoski Gregory Frederick
• Shah Manish K
• Leung Kin Hing

Classifications

• G06F15/80

  comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F15/17343

  wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture (reconfigurable processors arrays G06F15/7867) · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/20 Primary

  for access to input/output bus · CPC title