Method and system for reuse of partial bad block

Patent metadata

Field	Value
Publication number	US-12135883-B2
Application number	US-202217991137-A
Country	US
Kind code	B2
Filing date	Nov 21, 2022
Priority date	Jun 29, 2022
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

Provided herein is a memory device, a memory system including the memory device, and a method of operating the memory system. The memory device including a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks, peripheral circuits configured to perform a program operation on a memory block selected from among the plurality of memory blocks and configured to, when a program failure occurs during the program operation, move and store first data stored in a failed sub-block in which the program failure has occurred, among the plurality of sub-blocks, to a replacement block, among the plurality of memory blocks, and control logic configured to control the peripheral circuits to perform the program operation and generate bad block information from information about the failed sub-block.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array including a plurality of memory blocks, each of the plurality of memory blocks including a plurality of sub-blocks;
peripheral circuits configured to perform a program operation on a memory block selected from among the plurality of memory blocks and configured to, when a program failure occurs during the program operation, move and store first data stored in a failed sub-block in which the program failure has occurred, among the plurality of sub-blocks, to a replacement block, among the plurality of memory blocks; and
control logic configured to control the peripheral circuits to perform the program operation and generate bad block information from information about the failed sub-block,
wherein each of the plurality of memory blocks comprises a plurality of physical pages corresponding to a plurality of word lines, each of the plurality of sub-blocks comprises one or more of the plurality of physical pages, and the one or more of the plurality of physical pages comprised in each of the plurality of sub-blocks are different from each other, and
wherein the peripheral circuits move and store the first data, stored in the failed sub-block, to the replacement block, and thereafter erase the failed sub-block.

2. The memory device according to claim 1 , wherein each of the plurality of memory blocks comprises a plurality of memory cell strings, and a plurality of memory cells included in each of the plurality of memory cell strings are grouped into a plurality of groups respectively corresponding to the plurality of sub-blocks.

3. The memory device according to claim 1 , wherein the plurality of memory blocks comprise a plurality of normal memory blocks and the replacement block.

4. The memory device according to claim 1 , wherein the peripheral circuits move and store second data, stored in remaining sub-blocks except for the failed sub-block among the plurality of sub-blocks included in the selected memory block, to the replacement block during an operation of moving and storing the first data stored in the failed sub-block to the replacement block.

5. The memory device according to claim 4 , wherein:
the peripheral circuits move and store the first data and the second data to the replacement block and thereafter erase all of the plurality of sub-blocks included in the selected memory block.

6. A memory system, comprising:
a memory device comprising a plurality of memory blocks, wherein each of the plurality of memory blocks include a plurality of sub-blocks, and wherein the memory device is configured to output information about a failed sub-block determined to be a bad block, among the plurality of sub-blocks, as bad block information; and
a memory controller configured to receive and store the bad block information, and control the memory device such that, during an overall operation of the memory device, sub-blocks other than the failed sub-block, determined to be the bad block based on the bad block information, are selected and the overall operation is performed on the selected sub-blocks,
wherein each of the plurality of memory blocks comprises a plurality of physical pages corresponding to a plurality of word lines, each of the plurality of sub-blocks comprises one are of the plurality of physical pages, and the one are of the plurality of physical pages comprised in each of the plurality of sub-blocks are different from each other,
wherein the memory device further comprises:
a memory cell array including the plurality of memory blocks;
peripheral circuits configured to perform a program operation on a memory block selected from among the plurality of memory blocks, and configured to, when a program failure occurs during the program operation, determine the failed sub-block in which the program failure has occurred, among the plurality of sub-blocks, to be the bad block and to move and store first data stored in the failed sub-block to a replacement block, among the plurality of memory blocks; and
control logic configured to control the peripheral circuits to perform the program operation and generate the bad block information from information about the failed sub-block, and
wherein the peripheral circuits move and store the first data, stored in the failed sub-block, to the replacement block and thereafter erase the failed sub-block.

7. The memory system according to claim 6 , wherein each of the plurality of memory blocks comprises a plurality of memory cell strings, and a plurality of memory cells included in each of the plurality of memory cell strings are grouped into a plurality of groups respectively corresponding to the plurality of sub-blocks.

8. The memory system according to claim 6 , wherein the plurality of memory blocks comprise a plurality of normal memory blocks and the replacement block.

9. The memory system according to claim 6 , wherein the peripheral circuits move and store second data, stored in remaining sub-blocks except for the failed sub-block among the plurality of sub-blocks included in the selected memory block, to the replacement block during an operation of moving and storing the first data stored in the failed sub-block to the replacement block.

10. The memory system according to claim 9 , wherein the peripheral circuits move and store the first data and the second data to the replacement block and thereafter erase all of the plurality of sub-blocks included in the selected memory block.

11. A method of operating a memory device, comprising:
performing a program operation on a memory block selected from among a plurality of memory blocks, wherein each of the plurality of memory blocks, respectively, include a plurality of sub-blocks;
when a program failure occurs during the program operation, moving and storing first data stored in a failed sub-block in which the program failure has occurred, among the plurality of sub-blocks in the selected memory block, to a replacement block;
erasing the failed sub-block; and
registering the failed sub-block as a bad block,
wherein each of the plurality of memory blocks comprises a plurality of physical pages corresponding to a plurality of word lines, each of the plurality of sub-blocks comprises one or more of the plurality of physical pages, and the one or more of the plurality of physical pages comprised in each of the plurality of sub-blocks are different from each other.

12. The method according to claim 11 , wherein each of the plurality of memory blocks comprises a plurality of memory cell strings, and a plurality of memory cells included in each of the plurality of memory cell strings are grouped into a plurality of groups respectively corresponding to the plurality of sub-blocks.

13. The method according to claim 11 , wherein moving and storing the first data stored in the failed sub-block to the replacement block comprises:
moving and storing second data stored in remaining sub-blocks except for the failed sub-block among the plurality of sub-blocks included in the selected memory block to the replacement block.

14. The method according to claim 13 , wherein erasing the failed sub-block comprises:
erasing all of the plurality of sub-blocks included in the selected memory block.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G06F3/064 Primary

  Management of blocks · CPC title

• G06F3/0653

  Monitoring storage devices or systems · CPC title

• G06F3/0673

  Single storage device · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title