Technologies for trusted I/O protection of I/O data with header information

Patent metadata

Field	Value
Publication number	US-12135801-B2
Application number	US-202217820628-A
Country	US
Kind code	B2
Filing date	Aug 18, 2022
Priority date	Jun 20, 2016
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

Technologies for trusted I/O include a computing device having a hardware cryptographic agent, a cryptographic engine, and an I/O controller. The hardware cryptographic agent intercepts a message from the I/O controller and identifies boundaries of the message. The message may include multiple DMA transactions, and the start of message is the start of the first DMA transaction. The cryptographic engine encrypts the message and stores the encrypted data in a memory buffer. The cryptographic engine may skip and not encrypt header data starting at the start of message or may read a value from the header to determine the skip length. In some embodiments, the cryptographic agent and the cryptographic engine may be an inline cryptographic engine. In some embodiments, the cryptographic agent may be a channel identifier filter, and the cryptographic engine may be processor-based. Other embodiments are described and claimed.

First claim

The invention claimed is:

1. An apparatus comprising:
processor circuitry coupled to a memory;
an input/output (IO) controller to receive a plurality of IO messages from one or more IO devices;
a cryptographic engine configured to perform encryption operations on the plurality of IO messages to generate a respective plurality of encrypted messages and a corresponding plurality of authentication tags (ATs), the cryptographic engine to store the respective plurality of encrypted messages in an encrypted message buffer and to store the corresponding plurality of ATs in an authentication tag queue;
the processor circuitry to execute instructions to:
operate a trusted execution environment (TEE), the TEE to authenticate a next encrypted message of the plurality of encrypted messages based on a comparison with a corresponding AT in the authentication tag queue and, in response to a successful authentication, to decrypt the next encrypted message to generate a decrypted message to be accessible within the TEE;
determine whether the authentication tag queue and the encrypted-message buffer are synchronized; and
drop one or more of the encrypted messages from the encrypted message buffer when the authentication tag queue and the encrypted message buffer are not synchronized, wherein each AT stored in the authentication tag queue comprises one or more of a hash, a message length, or an authentication tag.

2. The apparatus of claim 1 , wherein to determine whether the authentication tag queue and the encrypted message buffer are synchronized comprises to determine whether an un-consumed entry of the authentication tag queue has been overwritten, wherein the hash comprises a predetermined number of bytes from a start of the encrypted message of the one or more encrypted messages.

3. The apparatus of claim 1 , wherein the processor circuitry to host a hardware cryptographic agent having the cryptographic engine, and wherein the processor circuitry is in communication with the trusted execution environment having an application enclave established by secure enclave support for the processor circuitry.

4. A method comprising:
receiving, by an input/output (IO) controller of a computing device, a plurality of IO messages from one or more IO devices;
performing, by a cryptographic engine of the computing device, encryption operations on the plurality of IO messages to generate a respective plurality of encrypted messages and a corresponding plurality of authentication tags (ATs), the cryptographic engine to store the respective plurality of encrypted messages in an encrypted message buffer and to store the corresponding plurality of ATs in an authentication tag queue;
authenticating, by a trusted execution environment (TEE) executed by a processor of the computing device, a next encrypted message of the plurality of encrypted messages based on a comparison with a corresponding AT in the authentication tag queue
decrypting the next encrypted message in response to a successful authentication to generate a decrypted message to be accessible within the TEE;
determining, by the processor of the computing device, whether the authentication tag queue and the encrypted message buffer are synchronized; and
dropping one or more of the encrypted messages from the encrypted message buffer when the authentication tag queue and the encrypted message buffer are not synchronized, wherein each AT stored in the authentication tag queue comprises one or more of a hash, a message length, or an authentication tag.

5. The method of claim 4 , wherein determining whether the authentication tag queue and the encrypted message buffer are synchronized comprises determining whether an un-consumed entry of the authentication tag queue has been overwritten, wherein the hash comprises a predetermined number of bytes from a start of the encrypted message of the one or more encrypted messages.

6. The method of claim 4 , wherein the processor comprises a hardware cryptographic agent having the cryptographic engine, and wherein the processor circuitry is in communication with the trusted execution environment having an application enclave established by secure enclave support for the processor circuitry.

7. At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
receiving, by an input/output (IO) controller of a computing device, a plurality of IO messages from one or more IO devices;
performing, by a cryptographic engine of the computing device, encryption operations on the plurality of IO messages to generate a respective plurality of encrypted messages and a corresponding plurality of authentication tags (ATs), the cryptographic engine to store the respective plurality of encrypted messages in an encrypted message buffer and to store the corresponding plurality of ATs in an authentication tag queue;
authenticating, by a trusted execution environment (TEE) executed by a processor of the computing device, a next encrypted message of the plurality of encrypted messages based on a comparison with a corresponding AT in the authentication tag queue
decrypting the next encrypted message in response to a successful authentication to generate a decrypted message to be accessible within the TEE;
determining, by the processor of the computing device, whether the authentication tag queue and the encrypted message buffer are synchronized; and
dropping one or more of the encrypted messages from the encrypted message buffer when the authentication tag queue and the encrypted message buffer are not synchronized, wherein each AT stored in the authentication tag queue comprises one or more of a hash, a message length, or an authentication tag.

8. The computer-readable medium of claim 7 , wherein determining whether the authentication tag queue and the encrypted message buffer are synchronized comprises determining whether an un-consumed entry of the authentication tag queue has been overwritten, wherein the hash comprises a predetermined number of bytes from a start of the encrypted message of the one or more encrypted messages.

9. The computer-readable medium of claim 7 , wherein the computing device comprises a processor coupled to a memory, wherein the processor comprises a hardware cryptographic agent having the cryptographic engine, and wherein the processor circuitry is in communication with the trusted execution environment having an application enclave established by secure enclave support for the processor circuitry.

Assignees

• Intel Corp

Inventors

• Desai Soham Jayesh
• Chhabra Siddhartha
• Xing Bin
• Pappachan Pradeep M
• Lal Reshma

Classifications

• H04L9/3242

  involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC · CPC title

• G06F21/6281

  at program execution time, where the protection is within the operating system · CPC title

• G06F21/51

  at application loading time, e.g. accepting, rejecting, starting or inhibiting executable software based on integrity or source reliability · CPC title

• G06F13/20

  for access to input/output bus · CPC title

• H04L9/0637

  Modes of operation, e.g. cipher block chaining [CBC], electronic codebook [ECB] or Galois/counter mode [GCM] · CPC title