High-performance input-output devices supporting scalable virtualization

Patent metadata

Field	Value
Publication number	US-11656916-B2
Application number	US-202117361932-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	May 2, 2017
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

Techniques for scalable virtualization of an Input/Output (I/O) device are described. An electronic device composes a virtual device comprising one or more assignable interface (AI) instances of a plurality of AI instances of a hosting function exposed by the I/O device. The electronic device emulates device resources of the I/O device via the virtual device. The electronic device intercepts a request from the guest pertaining to the virtual device, and determines whether the request from the guest is a fast-path operation to be passed directly to one of the one or more AI instances of the I/O device or a slow-path operation that is to be at least partially serviced via software executed by the electronic device. For a slow-path operation, the electronic device services the request at least partially via the software executed by the electronic device.

First claim

The invention claimed is:

1. An apparatus comprising:
a plurality of backend resources; and
one or more physical function base address registers (PF-BARs) to store one or more base addresses of one or more address ranges to be mapped to a plurality of memory-mapped input/output (MMIO) registers, including a first MMIO register to be accessed for a direct-path operation and a second MMIO register to be accessed for an intercepted-path operation; wherein hardware is to provide guest physical address to host physical address translation for the first MMIO register but not for the second MMIO register;
access for the direct-path operation is to be mapped by a virtual machine monitor (VMM) to an interface for a virtual device, the interface to be composed of one or more of the plurality of backend resources and to be identified by a process address-space identifier (PASID); and
access for the intercepted-path operation is to be intercepted by the VMM for emulation.

2. The apparatus of claim 1 , wherein the one or more PF-BARs includes a plurality of variable size PF-BARs.

3. The apparatus of claim 1 , wherein the one or more PF-BARs includes a plurality of non-contiguous PF-BARs.

4. The apparatus of claim 1 , wherein the one or more PF-BARs include at least one Peripheral Component Interconnect Express (PCIe) base address register.

5. The apparatus of claim 1 , wherein the access for the intercepted-path operation is to be intercepted by the VMM for emulation of a configuration space of the virtual device.

6. The apparatus of claim 1 , wherein the plurality of backend resources includes at least one of a transmission/reception (Tx/Rx) queue, a command queue, a Field Programmable Gate Array (FPGA) context, a set of one or more processing units, a Graphics Processing Unit (GPU) context, and a general-purpose computing on graphics processing unit (GPGPU) context.

7. A method comprising:
storing, in one or more physical function base address registers (PF-BARs), one or more base addresses of one or more address ranges to be mapped to a plurality of memory-mapped input/output (MMIO) registers, including a first MMIO register to be accessed for a direct-path operation and a second MMIO register to be accessed for an intercepted-path operation;
performing, by hardware, guest physical address to host physical address translation for the first MMIO register but not for the second MMIO register;
mapping, by a virtual machine monitor (VMM), access for the direct-path operation to an interface for a virtual device, the interface to be composed of one or more of a plurality of backend resources and to be identified by a process address-space identifier (PASID); and
intercepting, by the VMM, access for the intercepted-path operation for emulation.

8. The method of claim 7 , wherein the one or more PF-BARs includes a plurality of variable size PF-BARs.

9. The method of claim 7 , wherein the one or more PF-BARs includes a plurality of non-contiguous PF-BARs.

10. The method of claim 7 , wherein the one or more PF-BARs include at least one Peripheral Component Interconnect Express (PCIe) base address register.

11. The method of claim 7 , wherein the access for the intercepted-path operation is to be intercepted by the VMM for emulation of a configuration space of the virtual device.

12. The method of claim 7 , wherein the plurality of backend resources includes at least one of a transmission/reception (Tx/Rx) queue, a command queue, a Field Programmable Gate Array (FPGA) context, a set of one or more processing units, a Graphics Processing Unit (GPU) context, and a general-purpose computing on graphics processing unit (GPGPU) context.

13. A non-transitory machine-readable medium storing instructions, which when executed by a machine, cause the machine to perform a method comprising:
storing, in one or more physical function base address registers (PF-BARs), one or more base addresses of one or more address ranges to be mapped to a plurality of memory-mapped input/output (MMIO) registers, including a first MMIO register to be accessed for a direct-path operation and a second MMIO register to be accessed for an intercepted-path operation;
performing, by hardware, guest physical address to host physical address translation for the first MMIO register but not for the second MMIO register;
mapping, by a virtual machine monitor (VMM), access for the direct-path operation to an interface for a virtual device, the interface to be composed of one or more of a plurality of backend resources and to be identified by a process address-space identifier (PASID); and
intercepting, by the VMM, access for the intercepted-path operation for emulation.

14. The non-transitory machine-readable medium of claim 13 , wherein the one or more PF-BARs includes a plurality of variable size PF-BARs.

15. The non-transitory machine-readable medium of claim 13 , wherein the one or more PF-BARs includes a plurality of non-contiguous PF-BARs.

16. The non-transitory machine-readable medium of claim 13 , wherein the one or more PF-BARs include at least one Peripheral Component Interconnect Express (PCIe) base address register.

17. The non-transitory machine-readable medium of claim 13 , wherein the access for the intercepted-path operation is to be intercepted by the VMM for emulation of a configuration space of the virtual device.

18. The non-transitory machine-readable medium of claim 13 , wherein the plurality of backend resources includes at least one of a transmission/reception (Tx/Rx) queue, a command queue, a Field Programmable Gate Array (FPGA) context, a set of one or more processing units, a Graphics Processing Unit (GPU) context, and a general-purpose computing on graphics processing unit (GPGPU) context.

Assignees

• Intel Corp

Inventors

• Kakaiya Utkarsh Y
• Sankaran Rajesh
• Kumar Sanjay
• Tian Kun
• Lantz Philip

Classifications

• H04L51/226 Primary

  Delivery according to priorities · CPC title

• H04L67/2885

  Hierarchically arranged intermediate devices, e.g. for hierarchical caching · CPC title

• G06F9/5077 Primary

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• H04L61/59

  using proxies for addressing · CPC title