Microfluidic chip and fabrication method

Patent metadata

Field	Value
Publication number	US-12134097-B2
Application number	US-202217684719-A
Country	US
Kind code	B2
Filing date	Mar 2, 2022
Priority date	Dec 30, 2021
Publication date	Nov 5, 2024
Grant date	Nov 5, 2024

Abstract

A microfluidic chip and a fabrication method of the microfluidic chip are provided. The microfluidic chip includes an array substrate, and a hydrophobic layer disposed on a side of the array substrate. The hydrophobic layer includes at least one through-hole, and a through-hole of the at least one through-hole penetrates through the hydrophobic layer along a direction perpendicular to a plane of the array substrate. The microfluidic chip also includes at least one hydrophilic structure. A hydrophilic structure of the at least one hydrophilic structure is disposed in the through-hole.

First claim

What is claimed is:

1. A microfluidic chip, comprising:
an array substrate, including:
a base substrate,
a circuit layer, disposed on a side of the base substrate, and
an electrode layer, disposed on a side of the circuit layer away from the base substrate, wherein the electrode layer includes a plurality of driving electrodes;

a hydrophobic layer, disposed on a side of the array substrate including the plurality of driving electrodes, wherein the hydrophobic layer includes at least one through-hole, and a through-hole of the at least one through-hole penetrates through the hydrophobic layer along a direction perpendicular to a plane of the array substrate; and
at least one hydrophilic structure, wherein a hydrophilic structure of the at least one hydrophilic structure is disposed in the through-hole,
wherein in a plane parallel to the base substrate, the at least one hydrophilic structure is disposed between adjacent two driving electrodes of the plurality of driving electrodes.

2. The microfluidic chip according to claim 1 , wherein:
along the direction perpendicular to the plane of the array substrate, the hydrophilic structure has a height of h1, and the through-hole has a height of h2, wherein h2>h1.

3. The microfluidic chip according to claim 2 , wherein:
h 2− h 1≥1 μm.

4. The microfluidic chip according to claim 1 , wherein:
a reaction material is disposed on a side of the hydrophilic structure away from the array substrate.

5. The microfluidic chip according to claim 4 , wherein:
along the direction perpendicular to the plane of the array substrate, a sum of a height of the reaction material and a height of the hydrophilic structure is less than a height of the through-hole.

6. A microfluidic chip, comprising:
an array substrate;
a hydrophobic layer, disposed on a side of the array substrate, wherein the hydrophobic layer includes at least one through-hole, and a through-hole of the at least one through-hole penetrates through the hydrophobic layer along a direction perpendicular to a plane of the array substrate; and
at least one hydrophilic structure, wherein a hydrophilic structure of the at least one hydrophilic structure is disposed in the through-hole, wherein:
the hydrophilic structure is made of a material including one or more of silicon oxide, silicon nitride, polyvinylpyrrolidone and sodium hydroxide.

7. A microfluidic chip, comprising:
an array substrate;
a hydrophobic layer, disposed on a side of the array substrate, wherein the hydrophobic layer includes at least one through-hole, and a through-hole of the at least one through-hole penetrates through the hydrophobic layer along a direction perpendicular to a plane of the array substrate; and
at least one hydrophilic structure, wherein a hydrophilic structure of the at least one hydrophilic structure is disposed in the through-hole,
wherein the array substrate includes:
a base substrate,
a circuit layer, disposed on a side of the base substrate, wherein the circuit layer includes a plurality of first transistors,
an electrode layer, disposed on a side of the circuit layer away from the base substrate, wherein the electrode layer includes a plurality of driving electrodes, and a driving electrode of the plurality of driving electrodes is electrically connected to a first transistor of the plurality of first transistors, and
an insulating layer, disposed on a side of the electrode layer away from the base substrate, wherein the hydrophobic layer is disposed on a side of the insulating layer away from the base substrate.

8. The microfluidic chip according to claim 7 , wherein:
in a plane parallel to the base substrate, the at least one hydrophilic structure is disposed between adjacent two driving electrodes of the plurality of driving electrodes.

9. The microfluidic chip according to claim 8 , wherein:
the circuit layer further includes at least one second transistor,
the electrode layer further includes at least one heating electrode, wherein a heating electrode of the at least one heating electrode is electrically connected to a second transistor of the at least one second transistor, and
along the direction perpendicular to the plane of the array substrate, the at least one hydrophilic structure at least partially overlaps the heating electrode.

10. The microfluidic chip according to claim 9 , wherein:
the heating electrode is made of a material including a metal.

11. A fabrication method of a microfluidic chip, comprising:
forming an array substrate by:
providing a base substrate,
forming a circuit layer on a side of the base substrate, and
forming an electrode layer on a side of the circuit layer away from the base substrate, wherein the electrode layer includes a plurality of driving electrodes;

forming a hydrophilic layer on a side of the array substrate including the plurality of driving electrodes;
forming a first photoresist pattern on a side of the hydrophilic layer away from the array substrate, wherein the first photoresist pattern corresponds to a region of a to-be-formed hydrophilic structure in the hydrophilic layer;
etching the hydrophilic layer using the first photoresist pattern as a mask to form at least one hydrophilic structure;
forming a hydrophobic layer on the side of the array substrate where the at least one hydrophilic structure is formed, wherein the hydrophobic layer includes at least one through-hole, along a direction perpendicular to a plane of the array substrate, a through-hole of the at least one through-hole penetrates through the hydrophobic layer, and a hydrophilic structure of the at least one hydrophilic structure and the first photoresist pattern are located in the through-hole,
wherein, in a plane parallel to the base substrate, the at least one hydrophilic structure is disposed between adjacent two driving electrodes of the plurality of driving electrodes; and

removing the first photoresist pattern.

12. The method according to claim 11 , wherein:
along the direction perpendicular to the plane of the array substrate, the hydrophilic structure has a height of h1, and the through-hole has a height of h2, wherein h2>h1.

13. The method according to claim 11 , further including:
pre-embedding a reaction material on a side of the hydrophilic structure away from the array substrate.

14. The method according to claim 13 , before removing the first photoresist pattern, further including:
forming a protective coating layer on a side of the hydrophobic layer away from the array substrate, wherein the protective coating layer covers the hydrophobic layer and the first photoresist pattern;
removing a portion of the protective coating layer covering the first photoresist pattern and the first photoresist pattern, to expose the hydrophilic structure;
soaking the side of the hydrophilic structure away from the array substrate in a reaction material, to pre-embed the reaction material on the side of the hydrophilic structure away from the array substrate; and
removing another portion of the protective coating layer covering the hydrophobic layer.

15. The method according to claim 14 , wherein:
the protective coating layer is made of parylene.

16. The method according to claim 11 , wherein:
the circuit layer includes a plurality of first transistors;
a driving electrode of the plurality of driving electrodes is electrically connected to a first transistor of the plurality of first transistors; and
forming the array substrate further includes forming an insulating layer on a side of the electrode layer away from the bas

Assignees

• Shanghai Tianma Micro Elect Co

Inventors

• Li Wei
• Lin Baiquan
• Zhang Kaidi
• Bai Yunfei
• Su Ping
• Xi Kerui
• Jia Zhenyu

Classifications

• B81C2201/053

  Depositing a protective layers · CPC title

• B81C2201/0198

  for making a masking layer · CPC title

• B81C2201/013

  Etching · CPC title

• B81C1/00714

  Treatment for improving the physical properties not provided for in groups B81C1/0065 - B81C1/00706 · CPC title

• B81B2203/0353

  Holes · CPC title