Package embedded magnetic inductor structures and manufacturing techniques for 5-50 MHZ SMPS operations

Patent metadata

Field	Value
Publication number	US-12132015-B2
Application number	US-201916665682-A
Country	US
Kind code	B2
Filing date	Oct 28, 2019
Priority date	Oct 28, 2019
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

Embodiments include inductors and methods to form the inductors. An inductor includes a substrate layer that surrounds a magnetic layer, where the magnetic layer is embedded between the substrate layer. The inductor also includes a dielectric layer that surrounds the substrate and magnetic layers, where the dielectric layer fully embeds the substrate and magnetic layers. The inductor further includes a first conductive layer over the dielectric layer, a second conductive layer below the dielectric layer, and a plurality of plated-through-hole (PTH) vias in the dielectric and substrate layers. The PTH vias vertically extend from the first conductive layer to the second conductive layer, and the magnetic layer in between the PTH vias. The magnetic layer may have a thickness that is substantially equal to a thickness of the substrate layer, where the thickness of the magnetic layer is less than a thickness defined between the first and second conductive layers.

First claim

What is claimed is:

1. An inductor, comprising:
a substrate layer that surrounds a magnetic layer, wherein the magnetic layer is embedded between the substrate layer, and wherein the magnetic layer has a sidewall;
a dielectric layer that surrounds the substrate layer and the magnetic layer, wherein the dielectric layer fully embeds the substrate layer and the magnetic layer, and wherein the dielectric layer is in contact with the sidewall of the magnetic layer;
a first conductive layer over the dielectric layer;
a second conductive layer below the dielectric layer; and
a plurality of plated-through-hole (PTH) vias in the dielectric layer and the substrate layer, wherein the plurality of PTH vias vertically extend from the first conductive layer to the second conductive layer, wherein the magnetic layer is laterally between the plurality of PTH vias, and wherein each one of the plurality of PTH vias is in contact with the substrate layer.

2. The inductor of claim 1 , wherein the magnetic layer has a thickness that is substantially equal to a thickness of the substrate layer, and wherein the thickness of the magnetic layer is less than a thickness defined between a top surface of the second conductive layer to a bottom surface of the first conductive layer.

3. The inductor of claim 1 , further comprising:
a resin material in the plurality of PTH vias, wherein the plurality of PTH vias fully surround the resin material; and
an opening between the first conductive layer and the plurality of PTH vias, wherein the opening is over the dielectric layer and the magnetic layer, and wherein the opening exposes a portion of a top surface of the dielectric layer.

4. The inductor of claim 3 , wherein the resin material has a top surface that is substantially coplanar to a top surface of the first conductive layer, and wherein the resin material has a bottom surface that is substantially coplanar to a bottom surface of the second conductive layer.

5. The inductor of claim 3 , wherein the dielectric layer separates outer sidewalls of the magnetic layer from sidewalls of the substrate layer, wherein the first conductive layer is directly on a top surface of the dielectric layer, wherein the second conductive layer is directly on a bottom surface of the dielectric layer, wherein the dielectric layer has a first thickness and a second thickness, wherein the first thickness is defined from top surfaces of the magnetic and substrate layers to the top surface of the dielectric layer, wherein the second thickness is defined from bottom surfaces of the magnetic and substrate layers to the bottom surface of the dielectric layer, and wherein the first thickness of the dielectric layer is substantially equal to the second thickness of the dielectric layer.

6. The inductor of claim 1 , wherein the plurality of PTH vias conductively couple the first conductive layer to the second conductive layer, wherein the plurality of PTH vias have a plurality of sidewalls, and wherein the plurality of sidewalls are a plurality of substantially vertical sidewalls or a plurality of tapered sidewalls.

7. The inductor of claim 1 , wherein the magnetic layer has a top surface that is substantially coplanar to a top surface of the substrate layer.

8. The inductor of claim 1 , wherein the magnetic layer includes ferroelectric materials, conductive materials, or epoxy materials.

9. The inductor of claim 1 , wherein the first and second conductive layers have a toroidal shape, a solenoid shape, or a rectangular shape, and wherein the magnetic layer has a rectangular shape, a circular shape, or a rounded-edge shape.

10. An inductor, comprising:
a substrate layer that surrounds a magnetic layer, wherein the magnetic layer is embedded between the substrate layer, and wherein the magnetic layer has a sidewall;
a dielectric layer that surrounds the substrate layer and the magnetic layer, wherein the dielectric layer fully embeds the substrate layer and the magnetic layer, and wherein the dielectric layer is in contact with the sidewall of the magnetic layer;
a first conductive layer over the dielectric layer;
a second conductive layer below the dielectric layer;
a plurality of plated-through-hole (PTH) vias in the dielectric layer and the substrate layer, wherein the plurality of PTH vias vertically extend from the first conductive layer to the second conductive layer, and wherein the magnetic layer is laterally between the plurality of PTH vias;
a resin material in the plurality of PTH vias, wherein the plurality of PTH vias fully surround the resin material; and
an opening between the first conductive layer and the plurality of PTH vias, wherein the opening is over the dielectric layer and the magnetic layer, and wherein the opening exposes a portion of a top surface of the dielectric layer, wherein the dielectric layer separates outer sidewalls of the magnetic layer from sidewalls of the substrate layer, wherein the first conductive layer is directly on a top surface of the dielectric layer, wherein the second conductive layer is directly on a bottom surface of the dielectric layer, wherein the dielectric layer has a first thickness and a second thickness, wherein the first thickness is defined from top surfaces of the magnetic and substrate layers to the top surface of the dielectric layer, wherein the second thickness is defined from bottom surfaces of the magnetic and substrate layers to the bottom surface of the dielectric layer, and wherein the first thickness of the dielectric layer is substantially equal to the second thickness of the dielectric layer.

Assignees

• Intel Corp

Inventors

• Lambert William J
• Chavali Sri Chaitra Jyotsna

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title