Power semiconductor apparatus

Patent metadata

Field	Value
Publication number	US-12132014-B2
Application number	US-202017622588-A
Country	US
Kind code	B2
Filing date	Jul 8, 2020
Priority date	Jul 24, 2019
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A power semiconductor apparatus provided with a first conductor section connected to a direct-current terminal for transmitting direct-current power; a second conductor section connected to an alternating-current terminal for transmitting alternating-current power; a semiconductor element which is disposed between the first conductor section and the second conductor section and is for converting the direct-current power to the alternating-current power; and an interposition section disposed between the first conductor section and the second conductor section, in which the interposition section has a first conductor layer connected to the first conductor section, a second conductor layer connected to the second conductor section, and a plurality of insulation layers disposed between the first conductor layer and the second conductor layer, with one or a plurality of third conductor layers sandwiched between the plurality of insulation layers.

First claim

The invention claimed is:

1. A power semiconductor apparatus, comprising:
a first conductor section connected to a direct-current terminal for transmitting direct-current power;
a second conductor section connected to an alternating-current terminal for transmitting alternating-current power;
a semiconductor element which is disposed between the first conductor section and the second conductor section and is for converting the direct-current power to the alternating-current power;
an interposition section disposed between the first conductor section and the second conductor section; and
a sealing resin which seals each of the components of the power semiconductor apparatus,

wherein
the interposition section has
a first conductor layer connected to the first conductor section,
a second conductor layer connected to the second conductor section, and
a plurality of insulation layers disposed between the first conductor layer and the second conductor layer, with one or a plurality of third conductor layers sandwiched between the plurality of insulation layers to be electrically insulated from the first conductor layer and the second conductor layer, characterized in that the one or the plurality of third conductor layers are not electrically connected to the first conductor section or the second conductor section.

2. The power semiconductor apparatus according to claim 1 , wherein
the plurality of insulation layers includes a first insulation layer disposed between the first conductor layer and the one or a plurality of third conductor layers, and a second insulation layer disposed between the second conductor layer and the one or the plurality of third conductor layers.

3. The power semiconductor apparatus according to claim 2 , wherein
the plurality of insulation layers further includes a third insulation layer disposed between the plurality of the third conductor layers.

4. The power semiconductor apparatus according to claim 1 , wherein the interposition section is formed using a printed circuit board.

5. The power semiconductor apparatus according to claim 1 , wherein the interposition section is disposed so as to surround the perimeter of the semiconductor element in a plane orthogonal to a direction in which the first conductor section and the second conductor section overlap.

6. The power semiconductor apparatus according to claim 1 , further comprising:
an electrically-conductive spacer disposed between the first conductor section and the semiconductor element or between the second conductor section and the semiconductor element.

Assignees

• Hitachi Ltd

Inventors

• Kusukawa Junpei
• Ide Eiichi

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07354

  changes in dispositions · CPC title

• H10W72/07352

  changes in structures or sizes · CPC title

• H10W72/347

  Dispositions of multiple die-attach connectors · CPC title