Display driving circuit, host, and display system including display driving circuit and host

Patent metadata

Field	Value
Publication number	US-12131696-B2
Application number	US-202318351177-A
Country	US
Kind code	B2
Filing date	Jul 12, 2023
Priority date	Jul 27, 2022
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

A display system includes a host configured to transfer image data respectively corresponding to a plurality of frames through a main channel, and to transfer a synchronization signal that synchronizes a clock signal of the host with a clock signal of the display driving circuit through an auxiliary channel, a display panel configured to display the image data, and a display driving circuit configured to generate control signals driving the display panel, based on the synchronization signal received through the auxiliary channel. The host is configured to transfer the synchronization signal including a first synchronization signal and a second synchronization signal that is different from the first synchronization signal, to the display driving circuit, through the auxiliary channel.

First claim

What is claimed is:

1. A display system comprising:
a host configured to transfer image data respectively corresponding to a plurality of frames through a main channel, and to transfer a synchronization signal that synchronizes a clock signal of the host with a clock signal of the display driving circuit, the synchronization signal transferred through an auxiliary channel;
a display panel configured to display the image data; and
a display driving circuit configured to generate control signals driving the display panel, based on the synchronization signal received through the auxiliary channel,
wherein the host is configured to transfer the synchronization signal that includes a first synchronization signal and a second synchronization signal that is different from the first synchronization signal, to the display driving circuit, through the auxiliary channel.

2. The display system of claim 1 , wherein at least one of a pulse width, a number of pulses, and a pulse pattern of the first synchronization signal is different from a respective one of the second synchronization signal.

3. The display system of claim 1 , wherein, in response to at least one of the plurality of frames being in a low power mode, the display driving circuit does not receive the image data through the main channel during the frame in the low power mode, but receives the synchronization signal through the auxiliary channel.

4. The display system of claim 1 , wherein
each of the plurality of frames comprises a plurality of sub-frames, and
the host is configured to generate third synchronization signals respectively corresponding to the plurality of sub-frames, and
to transfer, to the display driving circuit, the third synchronization signal through the auxiliary channel.

5. The display system of claim 4 , wherein the display driving circuit is configured to generate the control signal controlling an emission time of pixels of the display panel, based on the third synchronization signal.

6. The display system of claim 4 , wherein at least one of a pulse width, a number of pulses, and a pulse pattern of each of the first synchronization signal, the second synchronization signal, and the third synchronization signal is different from respective others thereof.

7. The display system of claim 1 , wherein the display driving circuit is configured to determine whether at least one error has occurred in a process of receiving the synchronization signal, based on a number of second synchronization signals received between a first reception time corresponding to the first synchronization signal being received and a second reception time corresponding to the first synchronization signal being received after the first reception time.

8. The display system of claim 7 , wherein,
in response to the number of second synchronization signals received between the first reception time and the second reception time matching a reference number stored in the display driving circuit, the display driving circuit is configured to determine that no error occurred in the process of receiving the synchronization signal, and
in response to the number of second synchronization signals received between the first reception time and the second reception time not matching the reference number, the display driving circuit is configured to determine that at least one error has occurred in the process of receiving the synchronization signal.

9. The display system of claim 8 , wherein,
in response to the display driving circuit determining that at least one error has occurred in the process of receiving the synchronization signal,
the display driving circuit is configured to control an emission time of pixels included in the display panel, based on a difference between the reference number and a number of second synchronization signals received between the first reception time and the second reception time.

10. The display system of claim 8 , wherein, in response to the display driving circuit determining that at least one error has occurred in the process of receiving the synchronization signal, the display driving circuit is configured to transfer a determination result to the host.

11. The display system of claim 8 , wherein,
in response to the display driving circuit determining that at least one error has occurred in the process of receiving the synchronization signal, and in response to the difference between the number of second synchronization signals received between the first reception time and the second reception time and the reference number, being less than a threshold value,
the display driving circuit is configured to control an emission time of pixels included in the display panel, based on the difference, and
in response to the difference being greater than or equal to the threshold value, the display driving circuit transfers the difference and the determination result to the host.

12. A display driving circuit configured to operate in a normal mode of a video mode and a low power mode, the display driving circuit comprising:
an interface configured to receive, in the normal mode, image data from a host through a main channel, and to receive, through an auxiliary channel in the normal mode and the low power mode, a first synchronization signal and a second synchronization signal that is different from the first synchronization signal;
a data processor configured to receive the image data from the interface and convert the image data; and
a timing controller configured to generate control signals driving a display panel based on the first synchronization signal and on the second synchronization signal.

13. The display driving circuit of claim 12 , wherein the timing controller comprises:
a detector configured to distinguish the first synchronization signal from the second synchronization signal;
a counter configured to count a number of detections, which is a number of second synchronization signals received between a first reception time corresponding to the first synchronization signal being received and a second reception time corresponding to the first synchronization signal being received after the first reception time;
a comparator configured to compare the number of detections to a reference number; and
an adjuster configured to determine whether at least one error has occurred in a process of receiving at least one of the first synchronization signal and the second synchronization signal, based on a comparison result of the comparator.

14. The display driving circuit of claim 13 , wherein, in response to determining that at least one error has occurred in the process of receiving at least one of the first synchronization signal and the second synchronization signal, the adjuster is configured to control an emission time of pixels included in the display panel based on a difference between the number of detections and the reference number.

15. The display driving circuit of claim 13 , wherein, in response to determining that at least one error has occurred in the process of receiving at least one of the first synchronization signal and the second synchronization signal, the adjuster is configured to transfer a determination result to the host.

16. The display driving circuit of claim 12 , wherein
the timing controller is configured to receive a third synchronization signal transferred from the host to the interface through the auxiliary channel, and
at least one of a pulse width, a number of pulses, and a pulse pattern of each of the first synchronization signal, the second synchronization signal, and the third synchron

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Changju
• Kwon Kyounghwan
• Huh Junho

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2370/045

  using multiple communication channels, e.g. parallel and serial · CPC title

• G09G5/006

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title