Resetting control signal generation circuitry, method and module, and display device

Patent metadata

Field	Value
Publication number	US-12131685-B2
Application number	US-202117765399-A
Country	US
Kind code	B2
Filing date	May 18, 2021
Priority date	Jun 4, 2020
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

The present disclosure provides a resetting control signal generation circuitry, a resetting control signal generation method, a resetting control signal generation module and a display device. The resetting control signal generation circuitry includes a resetting control signal output end, a first node control circuitry, a second node control circuitry, a first output circuitry and a second output circuitry. The first output circuitry is configured to enable the resetting control signal output end to be electrically coupled to or electrically decoupled from a first voltage end under the control of a potential at a first node. The second output circuitry is configured to enable the resetting control signal output end to be electrically coupled to or electrically decoupled from a second voltage end under the control of a potential at a second node.

First claim

What is claimed is:

1. A resetting control signal generation circuitry for prolonging service life of a display device light emitting element having an anode, by turning on the circuitry when a light-emission control transistor is turned off, and turning off the circuitry when the light-emission control transistor is turned on, to maintain a voltage sufficiently long for resetting the anode, the circuitry comprising a resetting control signal output, a first node control circuitry, a second node control circuitry, a first output circuitry and a second output circuitry, wherein
the first node control circuitry is configured to control a potential at a first node and maintain the potential at the first node;
the second node control circuitry is configured to control a potential at a second node and maintain the potential at the second node;
the first output circuitry is electrically coupled to the first node, the resetting control signal output and a first voltage, and configured to enable the resetting control signal output to be electrically coupled to or electrically decoupled from the first voltage under the control of the potential at the first node;
the second output circuitry is electrically coupled to the second node, the resetting control signal output and a second voltage, and configured to enable the resetting control signal output to be electrically coupled to or electrically decoupled from the second voltage under the control of the potential at the second node, and the first output circuitry comprises a first output transistor and an output capacitor;
a control electrode of the first output transistor is electrically coupled to the first node, a first electrode of the first output transistor is electrically coupled to the first voltage, and a second electrode of the first output transistor is electrically coupled to the resetting control signal output;
a first terminal of the output capacitor is electrically coupled to the first node, and a second terminal of the output capacitor is electrically coupled to the first voltage;
the second output circuitry comprises a second output transistor, a control electrode of the second output transistor is electrically coupled to the second node, a first electrode of the second output transistor is electrically coupled to the resetting control signal output, and a second electrode of the second output transistor is electrically coupled to the second voltage; and
the first voltage is a low voltage, and the second voltage is a high voltage;
wherein the first node control circuitry is electrically coupled to a first clock signal, a second clock signal, the first node, the second node, a third node, the first voltage and the second voltage, and configured to control a potential at the third node in accordance with a first voltage signal and the first clock signal under the control of the first clock signal and the potential at the second node, control the potential at the first node in accordance with a second voltage signal under the control of the potential at the third node, a second clock signal and the potential at the second node, and maintain the potential at the first node;
the first voltage is configured to provide the first voltage signal, the second voltage is configured to provide the second voltage signal;
the second node control circuitry is electrically coupled to the third node, the first clock signal, an initial voltage, the second clock signal, the second node and the second voltage, and configured to control the potential at the second node in accordance with the second clock signal, an initial voltage signal and the second voltage signal under the control of the first clock signal, the second clock signal, and the potential at the third node; and
the initial voltage is configured to provide the initial voltage signal;
wherein the first node control circuitry comprises a third node control sub-circuitry, a fourth node control sub-circuitry, and a first node control sub-circuitry;
the third node control sub-circuitry is electrically coupled to the first clock signal, the first voltage, the second node, and the third node, and configured to write the first voltage signal into the third node under the control of the first clock signal and write the first clock signal into the third node under the control of the potential at the second node;
the fourth node control sub-circuitry is electrically coupled to the third node, the fourth node and the second clock signal, and configured to write the second clock signal into the fourth node under the control of the potential at the third node and control a potential at the fourth node in accordance with the potential at the third node; and
the first node control sub-circuitry is electrically coupled to the fourth node, the second clock signal and the first node, and configured to enable the fourth node to be electrically coupled to or electrically decoupled from and the first node under the control of the second clock signal and maintain the potential at the first node.

2. The resetting control signal generation circuitry according to claim 1 , wherein the third node control sub-circuitry comprises a first control transistor and a second control transistor;
a control electrode of the first control transistor is electrically coupled to the first clock signal, a first electrode of the first control transistor is electrically coupled to the first voltage, and a second electrode of the first control transistor is electrically coupled to the third node; and
a control electrode of the second control transistor is electrically coupled to the second node, a first electrode of the second control transistor is electrically coupled to the third node, and a second electrode of the second control transistor is electrically coupled to the first clock signal.

3. The resetting control signal generation circuitry according to claim 1 , wherein the fourth node control sub-circuitry comprises a third control transistor and a first capacitor;
a control electrode of the third control transistor is electrically coupled to the third node, a first electrode of the third control transistor is electrically coupled to the second clock signal, and a second electrode of the third control transistor is electrically coupled to the fourth node; and
a first terminal of the first capacitor is electrically coupled to the third node, and a second terminal of the first capacitor is electrically coupled to the fourth node.

4. The resetting control signal generation circuitry according to claim 1 , wherein the first node control sub-circuitry comprises a fourth control transistor and a fifth control transistor;
a control electrode of the fourth control transistor is electrically coupled to the second clock signal, a first electrode of the fourth control transistor is electrically coupled to the fourth node, and a second electrode of the fourth control transistor is electrically coupled to the first node; and
a control electrode of the fifth control transistor is electrically coupled to a second node, a first electrode of the fifth control transistor is electrically coupled to the first node, and a second electrode of the fifth control transistor is electrically coupled to the second voltage.

5. The resetting control signal generation circuitry according to claim 1 , wherein the second node control circuitry comprises a sixth control transistor, a seventh control transistor, an eighth control transistor and a third capacitor;
a control electrode of the sixth control transistor is electrically coupled to the first clock signal, a first electrode of the sixth control transistor is electrically coupled to the initial voltage, and a second electrode of the sixth control transistor is electrically coupled to the second node;
a control electrode

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhao Shuang
• Chen Wenbo
• Yang Zhongliu
• Chen Chenyu
• Lu Hongting
• Yang Jing
• Ren Yanping

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title