Pixel unit circuit, pixel circuit, method for driving pixel circuit and display device

US2020184892A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2020184892-A1
Application numberUS-201816087972-A
CountryUS
Kind codeA1
Filing dateFeb 12, 2018
Priority dateJul 17, 2017
Publication dateJun 11, 2020
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A pixel unit circuit includes a light emitting element, a first end being connected to a low level input end; a storage capacitor sub-circuit, a first end being connected to a DC voltage input end; a driving transistor, a gate electrode being connected to a second end of the storage capacitor sub-circuit, and a first electrode being connected to a second end of the light emitting element; a light emitting control sub-circuit, a control end being connected to a light emitting control line, the first end being connected to a high-level input end, and the second end being connected to a second electrode of the driving transistor, and configured to control whether the second electrode of the driving transistor is connected to the high level input end; and a charge compensation control sub-circuit, connected to a gate line, a data line and the gate electrode of the driving transistor.

First claim

Opening claim text (preview).

1 . A pixel unit circuit, comprising: a light emitting element, a first end of the light emitting element being connected to a low level input end; a storage capacitor sub-circuit, a first end of the storage capacitor module being connected to a DC voltage input end; a driving transistor, a gate electrode of the driving transistor being connected to a second end of the storage capacitor sub-circuit, and a first electrode of the driving transistor being connected to a second end of the light emitting element; a light emitting control sub-circuit, a control end of the light emitting control sub-circuit being connected to a light emitting control line, the first end of the light emitting control sub-circuit being connected to a high level input end, and the second end of the light emitting control sub-circuit being connected to a second electrode of the driving transistor, and configured to control whether the second electrode of the driving transistor receives a signal from the high level input end under the control of the light emitting control line; and a charge compensation control sub-circuit, connected to a gate line, a data line and the gate electrode of the driving transistor, and configured to control whether the gate electrode of the driving transistor receives a signal from the data line under the control of the gate line. 2 . The pixel unit circuit according to claim 1 , further comprising: a reset sub-circuit, connected to the light emitting control line, the first electrode of the driving transistor, and a reset voltage input end, and configured to control whether the first electrode of the driving transistor receives a signal from the reset voltage input end under the control of the light emitting control line. 3 . The pixel unit circuit according to claim 2 , wherein the reset sub-circuit comprises a reset switch transistor, a gate electrode of the reset switch transistor is connected to the light emitting control line, a first electrode of the reset switch transistor is connected to the first electrode of the driving transistor, a second electrode of the reset switch transistor is connected to the reset voltage input end. 4 . The pixel unit circuit according to claim 3 , wherein the light emitting control sub-circuit includes a light emitting control transistor, a gate electrode of the light emitting control transistor is connected to the light emitting control line, the first electrode of the light emitting control transistor is connected to the high level input end, and the second electrode of the light emitting control transistor is connected to the second electrode of the driving transistor, the light emitting control transistor is a p-type transistor, the reset switch transistor is an n-type transistor. 5 . The pixel unit circuit according to claim 3 , wherein the light emitting control sub-circuit includes a light emitting control transistor, a gate electrode of the light emitting control transistor is connected to the light emitting control line, the first electrode of the light emitting control transistor is connected to the high level input end, and the second electrode of the light emitting control transistor is connected to the second electrode of the driving transistor, the light emitting control transistor is an n-type transistor, the reset switch transistor is a p-type transistor. 6 . The pixel unit circuit according to claim 1 , further comprising: a potential control transistor, a gate electrode and a first electrode of the potential control transistor is connected to the first electrode of the driving transistor, the second electrode of the potential control transistor is grounded; the potential control transistor is a p-type transistor. 7 . The pixel unit circuit according to claim 1 , wherein the gate line comprises a first gate switch line and a second gate switch line; the charging compensation control sub-circuit comprises: a first charge compensation control transistor, a gate electrode of the first charge compensation control transistor being connected to the first gate switch line, a first electrode of the first charge compensation control transistor being connected to a gate electrode of the drive transistor, and a second electrode of the first charge compensation control transistor being connected to the data line; and a second charge compensation control transistor, a gate electrode of the second charge compensation control transistor being connected to the second gate switch line, a first electrode of the second charge compensation control transistor being connected to the data line, and a second electrode of the second charge compensation control transistor being connected to a gate electrode of the drive transistor; and the first charge compensation control transistor is an n-type transistor, and the second charge compensation control transistor is a p-type transistor. 8 . A method for driving the pixel unit circuit according to claim 1 , wherein the method comprises: in a charging compensation phase, under the control of a light emitting control line, controlling, by the light emitting control sub-circuit, a second electrode of a driving transistor to receive a signal from a high level input end; under the control of a gate line, controlling, by a charging compensation control sub-circuit, a data voltage Vdata on a data line to be written to a gate electrode of the driving transistor, such that the driving transistor is turned on until a potential at a first electrode of the driving transistor becomes Vdata-Vth, the driving transistor being operated in a constant current region; Vth being a threshold voltage of the driving transistor; and in a pixel light emitting phase, under the control of the light emitting control line, controlling, the light emitting control sub-circuit, the second electrode of the driving transistor to receive a signal from the high level input end, and the driving transistor being operated in a constant current region to drive the light emitting element to emit light. 9 . The method for driving the pixel unit circuit according to claim 8 , wherein the pixel unit circuit further comprises a reset sub-circuit, connected to the light emitting control line, the first electrode of the driving transistor, and a reset voltage input end, configured to control whether the first electrode of the driving transistor receives a signal from the reset voltage input end under the control of the light emitting control line, the reset voltage input end includes a ground end or a low level input end, before the charging compensation phase, the method for driving the pixel unit circuit further comprises: in a reset phase, under the control of the light emitting control line, controlling, the reset sub-circuit, the first electrode of the drive transistor to receive a signal from the reset voltage input end, to reset the potential at the first electrode of the drive transistor; and in the charging compensation phase and the pixel light emitting phase, under the control of the light emitting control line, controlling, the reset sub-circuit, the first electrode of the drive transistor not to receive a signal from the reset voltage input end. 10 . A pixel circuit, comprising a plurality of gate lines, a plurality of data lines, a plurality of light emitting control lines, and a plurality of pixel unit circuits according to claim 1 , wherein the plurality of the pixel unit circuit are arranged in an array form, pixel unit circuits in a same row are connected to a same gate lines, pixel unit circuits in a same column are connected to a same data line. 11 . The pixel circuit according to claim 10 , wherein the pixel unit circuit furth

Assignees

Inventors

Classifications

  • G09G3/3258Primary

    with pixel circuitry controlling the voltage across the light-emitting element · CPC title

  • Display protection · CPC title

  • in the context of movement of objects on the screen or movement of the observer relative to the screen · CPC title

  • Reduction of after-image effects · CPC title

  • Improving the black level · CPC title

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What does patent US2020184892A1 cover?
A pixel unit circuit includes a light emitting element, a first end being connected to a low level input end; a storage capacitor sub-circuit, a first end being connected to a DC voltage input end; a driving transistor, a gate electrode being connected to a second end of the storage capacitor sub-circuit, and a first electrode being connected to a second end of the light emitting element; a lig…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G3/3258. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jun 11 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).