Memory system having system buffer and method of storing data by using the system buffer

Patent metadata

Field	Value
Publication number	US-12131061-B2
Application number	US-202117506931-A
Country	US
Kind code	B2
Filing date	Oct 21, 2021
Priority date	Apr 16, 2021
Publication date	Oct 29, 2024
Grant date	Oct 29, 2024

Abstract

Memory systems and operating methods of the memory systems are disclosed. In an implementation, a memory system includes a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas, and a buffer manager configured to designate an address of a buffer area in which a defect occurs as a defect address by comparing a first parity bit for data stored in the system buffer with a second parity bit that is obtained by a computation based on the data stored in the system buffer, and block access to the buffer area designated as the defect address.

First claim

What is claimed is:

1. A memory system comprising:
a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas; and
a controller configured to:
extract a first parity bit for data to be stored in the system buffer and a second parity bit from the data stored in the buffer areas;
generate a flag bit according to a comparison between the first parity bit and the second parity bit;
increase a count of an address corresponding to a first flag bit indicating that a defect occurs in a buffer area in which the data is stored, in response to generating the first flag bit as the flag bit;
determine, among the addresses, the address as a defect address when the count of the address is equal to or greater than a reference number; and
block access to the buffer area corresponding to the defect address,
wherein the controller comprises:
a counter configured to store the count associated with the address corresponding to the first flag bit, and output the defect address; and
a defect address storage coupled to the counter and configured to store the defect address output from the counter.

2. The memory system of claim 1 , wherein the system buffer includes at least one of a static random access memory (SRAM), a dynamic random access memory (DRAM), a NAND memory, or a combination of two or more of the SRAM, DRAM, and NAND memory.

3. The memory system of claim 1 , wherein the controller stores the first parity bit and the flag bit in the system buffer.

4. The memory system of claim 3 , wherein the controller is configured to count a number of selected bits of the data to be written to the system buffer, and generate the first parity bit based on a counted value.

5. The memory system of claim 4 , wherein the controller is configured to generate a first value as the first parity bit in a case that the counted value is an odd number, and generate a second value as the first parity bit in a case that the counted value is an even number.

6. The memory system of claim 3 , wherein the controller is configured to count a number of selected bits of the data written to the system buffer, generate the second parity bit based on a counted value, and determine whether the second parity bit matches the first parity bit.

7. The memory system of claim 6 , wherein the controller is configured to generate a second flag bit indicating that there is no defect, as the flag bit, in a case that the second parity bit matches the first parity bit, and generate the first flag bit indicating that there is a defect, as the flag bit, in a case that the second parity bit does not match the first parity bit.

8. The memory system of claim 3 , wherein the controller is configured to detect an error bit using a hamming code for the data stored in the system buffer, and store the flag bit corresponding to the first flag bit indicating that there is a defect in a buffer area corresponding to the address where the error bit is detected.

9. The memory system of claim 3 , wherein the counter is configured to store the reference number set as a natural number greater than or equal to one, store the address corresponding to the flag bit indicating that there is a defect, and count a number of detections of the address corresponding to the first flag bit indicating that there is a defect.

10. The memory system of claim 3 , wherein the defect address storage is configured to store a plurality of addresses as a plurality of defect addresses in a case that the counter generates the plurality of addresses, and block access to buffer areas corresponding to the plurality of defect addresses in the system buffer.

11. The memory system of claim 3 , wherein the system buffer further includes buffer areas configured to store the second parity bit generated by the controller.

12. The memory system of claim 1 , wherein the controller replaces the defect address with an address of a buffer area that does not include a defect.

13. A memory system comprising:
a system buffer including buffer areas configured to store data to be forwarded or accessed, wherein addresses are allocated to the buffer areas; and
a controller configured to:
detect an address that includes a defect using a parity or a hamming code for data written to the system buffer, or using the hamming code that uses the parity; and
block access to the detected address,
wherein the controller performs a defect address detection operation using the hamming code on at least one address in response to a result of using the parity indicating that the at least one address includes a defect.

14. The memory system of claim 13 , wherein the controller is configured to omit performing the defect address detection operation in response to the result of using the parity indicating that there is no address that includes a defect.

15. A method of operating a memory system, the method comprising:
storing, by a system buffer, data in buffer areas included in the system buffer;
generating, by a controller, a first parity bit for data before being stored in the system buffer;
generating, by the controller, a second parity bit from the data stored in the buffer areas;
generating, by the controller, a flag bit according to a comparison between the first parity bit and the second parity bit;
increasing, by a counter of the controller, a count of an address corresponding to a first flag bit indicating that a defect occurs in a buffer area in which the data is stored, in response to generating the first flag bit as the flag bit;
storing, by the counter of the controller, the count associated with the address corresponding to the first flag bit;
determining, by the counter of the controller, the address as a defect address when the count of the address is equal to or greater than a reference number;
storing, by a defect address storage of the controller, the defect address output from the counter; and
blocking, by the defect address storage of the controller, access to the buffer area corresponding to the defect address.

16. The method of claim 15 , wherein the first parity bit is generated as a first value in a case that a number of selected bits included in the data before being stored in the system buffer is an odd number, and is generated as a second value in a case that the number of selected bits included in the data before being stored in the system buffer is an even number.

17. The method of claim 16 , wherein the second parity bit is generated as the first value in a case that the number of selected bits included in the data stored in the system buffer is an odd number, and is generated as the second value in a case that the number of selected bits included in the data stored in the system buffer is an even number.

18. The method of claim 15 , wherein labeling determining the address as the defect address comprises:
setting the reference number;
determining whether a number of instances where values of the first and second parity bits are different from each other is equal to or greater than the reference number; and
labeling the corresponding address as the defect address when the number of instances where the values of the first and second parity bits are different from each other is equal to or greater than the reference number.

19. The method of claim 18 , wherein the reference number is set as a natural number greater than or equal to one.

20. The method of claim 15 , further comprising, after blocking access to the buffer area corresponding to

Assignees

• Sk Hynix Inc

Inventors

• Jang In Jong

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1032

  Simple parity · CPC title

• G06F2212/7209

  Validity control, e.g. using flags, time stamps or sequence numbers · CPC title