Dram assist error correction mechanism for ddr sdram interface

Patent metadata

Field	Value
Publication number	US-2018046541-A1
Application number	US-201615286460-A
Country	US
Kind code	A1
Filing date	Oct 5, 2016
Priority date	Aug 15, 2016
Publication date	Feb 15, 2018
Grant date	—

Abstract

A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method includes conducting a memory transaction including multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller, detecting one or more errors using an ECC chip of the DRAM, determining a number of the bursts having the errors using the ECC chip of the DRAM, determining whether the number of the bursts having the errors is greater than a threshold number, determining a type of the errors, and directing the memory controller based on the determined type of the errors, wherein the DRAM includes a single ECC chip per memory channel.

First claim

What is claimed is:

1 . A method of correcting a memory error of a dynamic random-access memory module (DRAM) using a double data rate (DDR) interface, the method comprising:
conducting a memory transaction comprising multiple bursts with a memory controller to send data from data chips of the DRAM to the memory controller; detecting one or more errors using an ECC chip of the DRAM; determining a number of the bursts having the errors using the ECC chip of the DRAM; determining whether the number of the bursts having the errors is greater than a threshold number; determining a type of the errors; and directing the memory controller based on the determined type of the errors, wherein the DRAM comprises a single ECC chip per memory channel.

2 . The method of claim 1 , wherein detecting the one or more errors using the ECC chip of the DRAM comprises performing a parity check for each of the bursts using the ECC chip.

3 . The method of claim 1 , further comprising directing the memory controller to retry a memory read from the DRAM when the number of the bursts having errors is not greater than the threshold number.

4 . The method of claim 3 , further comprising detecting an additional error when the memory controller retries the memory read; and
determining whether the additional error has an error pattern that is the same as the detected one or more errors.

5 . The method of claim 4 , further comprising directing the memory controller to again retry a memory read from the DRAM when it is determined that the additional error has an error pattern that is different than the detected one or more errors.

6 . The method of claim 4 , further comprising:
identifying a hard error when it is determined that the additional error has a same error pattern as the detected one or more errors; directing the memory controller to assist the DRAM in error correction; and logging an address of the error.

7 . The method of claim 1 , further comprising determining whether the one or more errors correspond to a same pin of a same chip when the number of the bursts having the errors is greater than the threshold number.

8 . The method of claim 7 , further comprising determining the error corresponds to a DQ failure when it is determined that the one or more errors correspond to a same pin of a same chip of the DRAM; and
determining the one or more errors correspond to a chip failure when it is determined that the one or more errors do not correspond to the same pin of the same chip.

9 . The method of claim 8 , wherein the directing the memory controller comprises directing the memory controller to assist in chipkill detection when the one or more errors correspond to the DQ failure or to the chip failure.

10 . The method of claim 1 , further comprising determining whether the one or more errors correspond to more than one chip of the DRAM when the number of the bursts having the errors is greater than the threshold number;
marking a corresponding chip of the DRAM as erased when it is determined that the one or more errors correspond to a same chip of the DRAM; and identifying a fatal error when it is determined that the one or more errors correspond to more than one chip of the DRAM. cm 11 . The method of claim 1 , further comprising determining whether another chip of the DRAM has been previously erased when the number of the bursts having the errors is greater than the threshold number; and identifying a fatal error when the another chip of the DRAM has been previously erased.

12 . A dynamic random-access memory module (DRAM) configured to communicate with a memory controller via a double data rate (DDR) interface, the DRAM comprising:
two memory channels, each memory channel comprising:
multiple data chips configured to store data thereon, and configured to deliver the data to the memory controller once during each of multiple bursts corresponding to a single memory transaction; and
a single error-correcting code (ECC) chip configured to determine a number of the multiple bursts having a memory error corresponding to one or more of the data chips.

13 . The DRAM of claim 12 , wherein the ECC chip is configured to detect an error, and is configured to determine a type of the detected error as one of a DQ failure, a chip failure, a soft error, or a hard error.

14 . The DRAM of claim 13 , wherein the ECC chip is configured to direct the memory controller to assist in chipkill detection or to assist in error correction depending on the determined type of the detected error.

15 . The DRAM of claim 12 , wherein the ECC chip is configured to issue a command to the memory controller when the ECC chip has detected an error such that the memory controller performs an information readout of the ECC chip.

16 . The DRAM of claim 12 , wherein the DRAM further comprises a single pin coupled to the ECC chip that is configured to alert the memory controller during the memory transaction when the ECC has detected an error by using a 1-bit ECC flag.

17 . The DRAM of claim 12 , wherein the data chips and the ECC chip are configured to deliver an additional burst, which is in addition to the multiple bursts, to the memory controller during each memory transaction to provide readout information of the ECC chip to the memory controller.

18 . A memory system comprising:
a memory controller; and a dynamic random-access memory module (DRAM) comprising data chips and error-correcting code (ECC) chips, wherein each of the ECC chips are configured to correct some errors of a corresponding memory channel of the DRAM, and wherein the memory controller is configured to assist the ECC chips to correct other errors that the ECC chips are not able to correct.

19 . The memory system of claim 18 , wherein each of the ECC chips comprises a pin for sending a 1-bit ECC flag to the memory controller upon detecting an error.

20 . The memory system of claim 18 , wherein the DRAM comprises a plurality of memory channels, and
wherein each memory channel of the DRAM comprises a single one of the ECC chips.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Niu Dimin
• Chang Mu Tien
• Zheng Hongzhong
• Kim Hyun Joong
• Song Won Hyung
• Choi Jangseok

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C5/04

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title