Analog-to-digital conversion circuit and method having quick tracking mechanism

Patent metadata

Field	Value
Publication number	US-12126353-B2
Application number	US-202217945136-A
Country	US
Kind code	B2
Filing date	Sep 15, 2022
Priority date	Dec 9, 2021
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

The present invention discloses an analog-to-digital conversion circuit having quick tracking mechanism is provided. A positive and a negative capacitor arrays receive a positive and a negative input voltages and output a positive and a negative output voltages. A first and a second comparators performs comparison thereon respectively according to and not according to a reference voltage to generate a first and a second comparison results. A control circuit does not perform level-shifting when a difference between the positive and the negative output voltages is not within a predetermined range. The control circuit assigns the positive and the negative capacitor arrays a voltage up-tracking direction and a voltage down-tracking direction respectively to switch a capacitor enabling combination with digital codes according to the second comparison result, and outputs the digital codes as a digital output signal when the positive and the negative output voltages equal.

First claim

What is claimed is:

1. An analog-to-digital conversion (ADC) circuit having quick tracking mechanism, comprising:
a positive capacitor array configured to receive a positive input voltage and output a positive output voltage;
a negative capacitor array configured to receive a negative input voltage and output a negative output voltage;
a first comparator configured to compare the positive output voltage and the negative output voltage according to a reference voltage to generate a first comparison result;
a second comparator configured to compare the positive output voltage and the negative output voltage to generate a second comparison result; and
a control circuit configured to receive the first comparison result and the second comparison result;
wherein the control circuit, in an initial stage and according to the first comparison result, does not perform level-shifting when a difference between the positive output voltage and the negative output voltage is not within a predetermined range related to the reference voltage;
the control circuit assigns a voltage down-tracking direction and a voltage up-tracking direction respectively to the positive capacitor array and the negative capacitor array when the positive output voltage is larger than the negative output voltage, assigns the voltage up-tracking direction and the voltage down-tracking direction respectively to the positive capacitor array and the negative capacitor array when the negative output voltage is larger than the positive output voltage, switches a capacitor enabling combination of the positive capacitor array and the negative capacitor array according to the second comparison result in each of a plurality of switching stages after the initial stage by using a set of digital codes and outputs the corresponding set of digital codes as a digital output signal when the positive output voltage and the negative output voltage equal to each other.

2. The analog-to-digital conversion circuit of claim 1 , wherein the first comparator comprises:
a positive terminal comparator configured to compare the positive output voltage and the reference voltage to generate a positive terminal comparison result comprised by the first comparison result; and
a negative terminal comparator configured to compare the negative output voltage and the reference voltage to generate a negative terminal comparison result comprised by the first comparison result;
wherein the control circuit is configured to set a range between a positive value and a negative value of the reference voltage to be the predetermined range and determine whether the difference between the positive output voltage and the negative output voltage is within the predetermined range according to the first comparison result.

3. The analog-to-digital conversion circuit of claim 1 , wherein each of the positive capacitor array and the negative capacitor array comprises:
a plurality of capacitors each having a first terminal and a second terminal, the first terminal is configured to receive the positive input voltage or the negative input voltage and output the positive output voltage or the negative output voltage; and
a capacitor switching circuit electrically coupled to the capacitors and configured to electrically couple the second terminal to a common mode voltage in the initial stage;
the capacitor switching circuit, in each of the switching stages after the initial stage and according to the second comparison result, is further configured to electrically couple the second terminal of at least one of the capacitors to a negative reference voltage to enable the capacitor when being corresponding to the voltage down-tracking direction and electrically couple the second terminal of at least one of the capacitors to a positive reference voltage to enable the capacitor when being corresponding to the voltage up-tracking direction by using the set of digital codes.

4. The analog-to-digital conversion circuit of claim 1 , wherein each of the positive capacitor array and the negative capacitor array comprises:
a plurality of capacitor pairs each having a first unit capacitor and a second unit capacitor having the same capacitance, wherein each of the first unit capacitor and the second unit capacitor has a first terminal and a second terminal, the first terminal being configured to receive the positive input voltage or the negative input voltage and output the positive output voltage or the negative output voltage;
a capacitor switching circuit electrically coupled to the capacitor pairs and configured to electrically couple the second terminal of the first unit capacitor and the second unit capacitor of each of the capacitor pairs to a common mode voltage in the initial stage;
the capacitor switching circuit, in each of the switching stages after the initial stage and according to the second comparison result, is further configured to electrically couple the second terminal of the first unit capacitor of at least one of the capacitor pairs to a negative reference voltage to enable the capacitor pairs when being corresponding to the voltage down-tracking direction and electrically couple the second terminal of the second unit capacitor of at least one of the capacitor pairs to a positive reference voltage to enable the capacitor pairs when being corresponding to the voltage up-tracking direction by using the set of digital codes.

5. The analog-to-digital conversion circuit of claim 1 , wherein in the initial stage and according to the first comparison result, the control circuit performs positive level-shifting on a larger one of the positive output voltage and the negative output voltage and performs negative level-shifting on a smaller one of the positive output voltage and the negative output voltage when the difference between the positive output voltage and the negative output voltage is within the predetermined range related to the reference voltage;
the control circuit assigns the voltage down-tracking direction and the voltage up-tracking direction respectively to the positive capacitor array and the negative capacitor array when the positive output voltage is larger than the negative output voltage, assigns the voltage up-tracking direction and the voltage down-tracking direction respectively to the positive capacitor array and the negative capacitor array when the negative output voltage is larger than the positive output voltage, and switches a capacitor enabling combination of the positive capacitor array and the negative capacitor array according to the second comparison result in each of the switching stages after the initial stage by using the set of digital codes.

6. The analog-to-digital conversion circuit of claim 1 , wherein in the initial stage and according to the first comparison result, the control circuit performs positive level-shifting on the positive output voltage and performs negative level-shifting on the negative output voltage when the difference between the positive output voltage and the negative output voltage is within the predetermined range related to the reference voltage such that the positive output voltage is larger than the negative output voltage;
the control circuit assigns the voltage down-tracking direction and the voltage up-tracking direction respectively to the positive capacitor array and the negative capacitor array and switches a capacitor enabling combination of the positive capacitor array and the negative capacitor array according to the second comparison result in each of the switching stages after the initial stage by using the set of digital codes.

7. An analog-to-digital conversion method having quick tracking mechanism, comprising:
receiving a positive input voltage and outputting a positive output voltage b

Assignees

• Realtek Semiconductor Corp

Inventors

• Hong Wei-Cian

Classifications

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/462

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• H03M1/0863

  of switching transients, e.g. glitches · CPC title

• H03M1/34 Primary

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title