High electron mobility transistor and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-12125903-B2
Application number	US-202318371440-A
Country	US
Kind code	B2
Filing date	Sep 21, 2023
Priority date	Jul 9, 2019
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.

First claim

What is claimed is:

1. A method for fabricating high electron mobility transistor (HEMT), comprising:
forming a buffer layer on a substrate;
forming a barrier layer on the buffer layer;
forming a hard mask on the barrier layer;
performing an ion implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; and
removing a portion of the hard mask and a portion of the barrier layer to form a first trench, wherein a width of the first trench is less than a width of the doped region.

2. The method of claim 1 , further comprising:
forming a gate dielectric layer on the hard mask and into the first trench;
forming a gate electrode on the gate dielectric layer; and
forming a source electrode on a first side of the gate electrode and a drain electrode on a second side of the gate electrode, the first side being opposite the second side.

3. The method of claim 2 , further comprising:
removing the gate dielectric layer, the hard mask, and the barrier layer to form a second trench and a third trench adjacent to two sides of the gate electrode; and
forming the source electrode in the second trench and the drain electrode in the third trench.

4. The method of claim 1 , wherein the buffer layer comprises a group III-V semiconductor.

5. The method of claim 1 , wherein the buffer layer comprises gallium nitride (GaN).

6. The method of claim 1 , wherein the barrier layer comprise Al x Ga 1-x N.

7. The method of claim 1 , wherein the doped region comprises fluorine.

8. The method of claim 7 , wherein a concentration of fluorine decreases from the barrier layer to the buffer layer.

Assignees

• United Microelectronics Corp

Inventors

• Huang Shin-Chuan
• Yeh Chih-Tung
• Chang Chun-Ming
• Chen bo-rong
• Liao Wen-Jung
• Hou Chun-Liang

Classifications

• H10P30/208

  of electrically inactive species · CPC title

• H10D64/01358

  the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title