Selective carbon deposition on top and bottom surfaces of semiconductor substrates

US12125699B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12125699-B2
Application numberUS-202117359947-A
CountryUS
Kind codeB2
Filing dateJun 28, 2021
Priority dateJun 28, 2021
Publication dateOct 22, 2024
Grant dateOct 22, 2024

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature less than or about 4 eV is generated from the deposition gas. The methods further include depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, where the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1. Also described are semiconductor structures that include an as-deposited carbon-containing layer on the top and bottom surface of at least a first and second trench, where the carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than or about 3:1.

First claim

Opening claim text (preview).

The invention claimed is: 1. A semiconductor processing method comprising: providing a substrate to a reaction chamber, wherein the substrate comprises substrate trenches having a top surface and a bottom surface; flowing a deposition gas into a plasma excitation region of the reaction chamber, wherein the deposition gas comprises a carbon-containing gas and a nitrogen-containing gas; generating a deposition plasma from the deposition gas, wherein the deposition plasma is characterized by an electron temperature less than 4 eV; and depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trenches, wherein the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than 3:1. 2. The semiconductor processing method of claim 1 , wherein the deposition gas is argon free and helium free. 3. The semiconductor processing method of claim 1 , wherein the method further comprises heating the substrate to a temperature greater than 100° C. before the deposition of the carbon-containing layer. 4. The semiconductor processing method of claim 1 , wherein the method further comprises etching through at least a portion of the carbon-containing layer in the bottom surface of the substrate trenches, wherein the carbon-containing layer still covers the top surface of the substrate trenches. 5. The semiconductor processing method of claim 4 , wherein the method further comprises removing the carbon-containing layer from the substrate after the etching of the at least a portion of the carbon-containing layer in the bottom surface of the substrate trenches. 6. The semiconductor processing method of claim 1 , wherein the carbon-containing gas comprises methane and the nitrogen-containing gas comprises molecular nitrogen. 7. The semiconductor processing method of claim 1 , wherein the deposition plasma is generated by delivering RF power to the deposition gas, and wherein the RF power is characterized by a power of less than 300 Watts. 8. The semiconductor processing method of claim 1 , wherein the deposition plasma is characterized by a pressure of less than 10 mTorr. 9. The semiconductor processing method of claim 1 , wherein a temperature at the top surface of the trench is greater than 1° C. below the temperature at the bottom surface of the trench during deposition. 10. A semiconductor processing method comprising: providing a substrate to a reaction chamber, wherein the substrate comprises a first trench with a first aspect ratio greater than 2:1, and a second trench with a second aspect ratio less than 1:2, wherein each of the first trench and the second trench has a top surface and a bottom surface; heating the substrate to a temperature greater than 100° C.; flowing a deposition gas into a plasma excitation region of the reaction chamber, wherein the deposition gas comprises a carbon-containing gas and a nitrogen-containing gas; generating a deposition plasma from the deposition gas, wherein the deposition plasma is characterized by an electron temperature less than 4 eV; and depositing a carbon-containing layer on the heated substrate, wherein the as-deposited carbon-containing layer has a top surface-to-bottom surface thickness ratio of greater than 3:1 in both the first trench and the second trench. 11. The semiconductor processing method of claim 10 , wherein the method further comprises: etching through at least a portion of the carbon-containing layer in the bottom surface of the first trench and the second trench, wherein the carbon-containing layer still covers the top surface of the first trench and the second trench; and removing the carbon-containing layer from the substrate after the etching of the at least a portion of the carbon-containing layer in the bottom surface of the first trench and the second trench. 12. The semiconductor processing method of claim 10 , wherein the deposition plasma is characterized by an electron temperature less than 4 eV. 13. The semiconductor processing method of claim 10 , wherein the first trench is characterized by a first bottom width of less than 50 nm and the second trench is characterized by a second bottom width of greater than 100 nm. 14. The semiconductor processing method of claim 10 , wherein the carbon-containing layer is characterized by a top-surface thickness of greater than 5 nm, and a bottom-surface thickness of less than 1.6 nm. 15. The semiconductor processing method of claim 10 , wherein the carbon-containing layer comprises solid carbon.

Assignees

Inventors

Classifications

  • Thermal treatments, e.g. annealing or sintering · CPC title

  • in the presence of a plasma [PECVD] · CPC title

  • in via holes or trenches · CPC title

  • composed of carbon, e.g. alpha-C, diamond or hydrogen doped carbon · CPC title

  • using masks for insulating materials · CPC title

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What does patent US12125699B2 cover?
Semiconductor processing methods are described that include providing a substrate to a reaction chamber, where the substrate includes substrate trenches that have a top surface and a bottom surface. A deposition gas that includes a carbon-containing gas and a nitrogen-containing gas flows into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature…
Who is the assignee on this patent?
Applied Materials Inc
What technology area does this patent fall under?
Primary CPC classification H10P14/6902. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 22 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).