Bandwidth allocation

Patent metadata

Field	Value
Publication number	US-12124385-B2
Application number	US-202217976395-A
Country	US
Kind code	B2
Filing date	Oct 28, 2022
Priority date	Oct 28, 2022
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

Aspects of the disclosure are directed to allocating bandwidth. As may be implemented in accordance with one or more embodiments, respective amounts of bandwidth are allocated to respective application groups for each memory access cycle in a set of memory access cycles. Initial bonus bandwidth is provided to a first one of the application groups during one of the memory access cycles. The bonus bandwidth may include at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle. Additional bonus bandwidth is selectively provided to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused.

First claim

What is claimed is:

1. A method comprising:
for a set of memory access cycles, allocating respective amounts of bandwidth to respective application groups for each memory access cycle in the set,
providing initial bonus bandwidth to a first one of the application groups during one of the memory access cycles, the bonus bandwidth including at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle, and
selectively providing additional bonus bandwidth to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused; and providing memory access with a higher priority to accesses for the allocated amounts of bandwidth, relative to a lower priority given to accesses for the bonus bandwidth.

2. The method of claim 1 , including incrementing a value in a counter each time that bonus bandwidth is assigned to the first one of the application groups, wherein the maximum amount of bonus bandwidth is defined as a maximum number of counts in the counter, and wherein providing the additional bonus includes providing the additional bonus in response to the counter having a value that is below the maximum number of counts.

3. The method of claim 2 , further including decrementing the counter after the set of memory access cycles has passed.

4. The method of claim 2 , further including decrementing the counter in response to the first one of the application groups having not won arbitration during the set of memory access cycles.

5. The method of claim 1 , wherein selectively providing the additional bonus bandwidth to the first application group includes selecting to provide no bonus bandwidth in response to the maximum amount of bonus bandwidth being defined as an amount corresponding to the initial bonus bandwidth provided to the first application group.

6. The method of claim 1 , wherein selectively providing the additional bonus bandwidth includes providing more than one bonus access during one of the memory access cycles in response to bandwidth being available for more than one bonus access during the one of the memory access cycles.

7. The method of claim 1 , wherein providing the bonus bandwidth includes providing a bonus access to at least two of the application groups during one of the memory access cycles, in response to bandwidth being available for the at least two bonus accesses during the one of the memory access cycles.

8. The method of claim 1 , wherein allocating respective amounts of bandwidth to respective application groups includes allocating one access to each application group for each memory access cycle, and wherein providing the initial bonus bandwidth includes providing bonus access to the first one of the application groups after the first one of the application groups has been granted its allocated access during the one of the memory access cycles.

9. The method of claim 1 , wherein providing the bonus bandwidth and selectively providing the additional bandwidth includes providing memory accesses based on a hierarchy corresponding to a weighted priority assigned to respective ones of the application groups.

10. An apparatus comprising:
interface circuitry configured to facilitate memory access by respective application groups; and
allocation circuitry configured and arranged with the interface circuitry to allocate bandwidth to the respective application groups, by:
for a set of memory access cycles, allocating respective amounts of bandwidth to respective application groups for each memory access cycle in the set,
providing initial bonus bandwidth to a first one of the application groups during one of the memory access cycles, the bonus bandwidth including at least a portion of bandwidth allocated to and unused by one of the other respective application groups during the memory access cycle, and

selectively providing additional bonus bandwidth to the first application group during one of the memory access cycles based on the initial bonus bandwidth and a maximum amount of bonus bandwidth defined for the set of memory access cycles, in response to bandwidth allocated to one of the other respective application groups during the subsequent memory access cycle being unused, wherein the allocation circuitry is configured to provide memory accesses within the bandwidth allocated to each respective application group as a higher priority than memory accesses provided via bonus bandwidth.

11. The apparatus of claim 10 , wherein each of the memory access groups is allocated a single memory access during each of the memory access cycles, and bonus bandwidth is provided by providing an unused one of the allocated memory accesses as a bonus memory access, for one of the memory access cycles, to one of the application groups having used its allocated memory access for the one of the memory access cycles.

12. The apparatus of claim 10 , wherein the allocation circuitry is configured to:
store a data value indicative of a total amount of bonus bandwidth provided to each of the application groups during the set of memory access cycles; and
decrement the stored data value after the set of memory cycles has concluded.

13. The apparatus of claim 10 , further including a counter circuit, wherein the allocation circuitry is configured to increment a value in the counter circuit each time that bonus bandwidth is assigned to the first one of the application groups, wherein the maximum amount of bonus bandwidth is defined as a maximum number of counts in the counter circuit, and to provide the additional bonus by providing the additional bonus in response to the counter circuit having a value that is below the maximum number of counts.

14. The apparatus of claim 13 , wherein the allocation circuitry is configured to decrement the counter circuit in response to a condition selected from the group of: after the set of memory access cycles has passed, the first one of the application groups having not won arbitration during the set of memory access cycles, and a combination thereof.

15. The apparatus of claim 10 , wherein the allocation circuitry is configured to selectively provide the additional bonus bandwidth to the first application group by selecting to provide no bonus bandwidth in response to the maximum amount of bonus bandwidth being defined as an amount corresponding to the initial bonus bandwidth provided to the first application group.

16. The apparatus of claim 10 , wherein the allocation circuitry is configured to selectively provide the bonus bandwidth by providing more than one bonus access during one of the memory access cycles in response to bandwidth being available for the more than one bonus access during the one of the memory access cycles.

17. The apparatus of claim 10 , wherein the allocation circuitry is configured to selectively provide the bonus bandwidth by providing a bonus access to at least two of the application groups during one of the memory access cycles, in response to sufficient bandwidth being available during the one of the memory access cycles.

18. The apparatus of claim 10 , wherein the allocation circuitry is configured to allocate the respective amounts of bandwidth to the respective application groups by allocating one access to each application group for each memory access cycle, and to prov

Assignees

• Nxp Bv

Inventors

• Welker James Andrew
• Kumar Vaibhav
• Kaul Rohit Kumar
• Sethi Ankush

Classifications

• G06F13/18

  based on priority control (G06F13/1605 takes precedence) · CPC title

• G06F13/161

  with latency improvement · CPC title

• G06F9/5016

  the resource being the memory · CPC title

• G06F13/1626 Primary

  by reordering requests · CPC title

• G06F13/1663 Primary

  Access to shared memory · CPC title