Transmission failure feedback schemes for reducing crosstalk

Patent metadata

Field	Value
Publication number	US-12124329-B2
Application number	US-202318211472-A
Country	US
Kind code	B2
Filing date	Jun 19, 2023
Priority date	Aug 21, 2018
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

Systems, apparatuses, and methods for transmission failure feedback associated with a memory device are described. A memory device may detect errors in received data and transmit an indication of the error when detected. The memory device may receive data and checksum information for the data from a controller. The memory device may generate a checksum for the received data and may detect transmission errors. The memory device may transmit an indication of detected errors to the controller, and the indication may be transmitted using a line that is different than an error detection code (EDC) line. A low-speed tracking clock signal may also be transmitted by the memory device over a line different than the EDC line. The memory device may transmit a generated checksum to the controller with a time offset applied to the checksum signaled over the EDC line.

First claim

What is claimed is:

1. A method, comprising:
transmitting, from one or more controllers, an access command associated with data to be read from or written to an array of memory cells of a memory device; and
receiving, over an error detection code (EDC) line, information for detecting an error in the data corresponding to the access command, wherein the information for detecting the error in the data is received in accordance with a timing delay value that corresponds to a programmable delay.

2. The method of claim 1 , wherein the timing delay value is from a set of one or more timing delay values.

3. The method of claim 2 , wherein the set of one or more timing delay values are associated with a mode register of the memory device.

4. The method of claim 3 , further comprising:
transmit, to the memory device, a signal indicating the set of one or more timing delay values.

5. The method of claim 4 , wherein the signal indicating the set of one or more timing delay values is transmitted to the memory device during an initialization sequence.

6. The method of claim 4 , wherein the signal indicating the set of one or more timing delay values comprises a command configuring the mode register of the memory device.

7. The method of claim 1 , wherein the information for detecting the error in the data comprises a cyclic redundancy check (CRC) checksum.

8. An apparatus, comprising:
a memory device comprising an array of memory cells; and
one or more controllers coupled with the memory device and configured to:
transmit, to the memory device, an access command for data to be written to or read from the array of memory cells of the memory device; and
receive, from the memory device, a first signal comprising information for detecting an error in the data, wherein the first signal is received in accordance with a timing delay value that corresponds to a programmable delay.

9. The apparatus of claim 8 , wherein the timing delay value is from a set of one or more timing delay values.

10. The apparatus of claim 9 , wherein the set of one or more timing delay values are associated with a mode register of the memory device.

11. The apparatus of claim 10 , wherein the one or more controllers are further configured to:
transmit, to the memory device, a signal indicating the set of one or more timing delay values.

12. The apparatus of claim 11 , wherein the signal indicating the set of one or more timing delay values is transmitted to the memory device during an initialization sequence.

13. The apparatus of claim 11 , wherein the signal indicating the set of one or more timing delay values comprises a command configuring the mode register of the memory device.

14. The apparatus of claim 8 , wherein the information for detecting the error in the data comprises a cyclic redundancy check (CRC) checksum.

15. An apparatus, comprising:
one or more controllers configured to transmit, to a memory device, an access command for data to be written to or read from an array of memory cells; and
the memory device comprising the array of memory cells, the memory device configured to transmit, to the one or more controllers, a first signal comprising information for detecting an error in the data, wherein the first signal is received in accordance with a timing delay value that corresponds to a programmable delay.

16. The apparatus of claim 15 , wherein the timing delay value is from a set of one or more timing delay values.

17. The apparatus of claim 16 , wherein the set of one or more timing delay values are associated with a mode register of the memory device.

18. The apparatus of claim 17 , wherein the one or more controllers is further configured to transmit, to the memory device, a signal indicating the set of one or more timing delay values.

19. The apparatus of claim 18 , wherein the signal indicating the set of one or more timing delay values is transmitted to the memory device during an initialization sequence.

20. The apparatus of claim 18 , wherein the signal indicating the set of one or more timing delay values comprises a command configuring the mode register of the memory device.

Assignees

• Micron Technology Inc

Inventors

• Mayer Peter
• Hein Thomas
• Brox Martin
• Spirkl Wolfgang Anton
• Richter Michael Dieter

Classifications

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G06F3/0683

  Plurality of storage devices · CPC title

• G06F3/0658

  Controller construction arrangements · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title