Far infrared (FIR) sensor device and manufacturing method thereof and determination method of thickness of sensor dielectric layer thereof

Patent metadata

Field	Value
Publication number	US-12123779-B2
Application number	US-202217676656-A
Country	US
Kind code	B2
Filing date	Feb 21, 2022
Priority date	May 11, 2021
Publication date	Oct 22, 2024
Grant date	Oct 22, 2024

Abstract

The present invention provides a far infrared (FIR) sensor device formed on a substrate, wherein the FIR sensor device includes: a sensor region, which is formed on the substrate, and is configured to operably sense a far infrared signal; and a sensor dielectric layer, which is formed on the sensor region, wherein a thickness of the sensor dielectric layer is determined by a sacrificial metal layer.

First claim

What is claimed is:

1. A far infrared (FIR) sensor device, comprising:
a sensor region, which is formed on a substrate, and is configured to operably sense a far infrared signal; and
a sensor dielectric layer, which is formed on the sensor region, wherein a thickness of the sensor dielectric layer is determined by a sacrificial metal layer;
wherein the FIR sensor device is manufactured by a CMOS process, a periphery circuit is formed on the substrate, wherein the periphery circuit includes at least one metal oxide semiconductor (MOS) device and a plurality of metal layers, and wherein one of the plurality of metal layers and the sacrificial metal layer are formed by a same metal deposition process step.

2. The FIR sensor device of claim 1 , wherein the thickness of the sensor dielectric layer is determined by steps including:
forming the sensor dielectric layer on the sensor region with the thickness;
depositing the sacrificial metal layer on the sensor dielectric layer;
forming an intermediate dielectric layer on the sacrificial metal layer;
etching the intermediate dielectric layer by a first etch process step, wherein an etch rate of the first etch process step etching the intermediate dielectric layer is higher than an etch rate of the first etch process step etching the sacrificial metal layer, wherein the sacrificial metal layer is an etch stop layer of the first etch process step; and
etching the sacrificial metal layer by a second etch process step.

3. The FIR sensor device of claim 2 , further comprising a stop layer which is formed on the sensor dielectric layer.

4. The FIR sensor device of claim 3 , wherein the thickness of the sensor dielectric layer is determined further by a process step of depositing the stop layer between the sensor dielectric layer and the sacrificial metal layer;
wherein an etch rate of the second etch process step etching the sacrificial metal layer is higher than an etch rate of the second etch process step etching the stop layer, wherein the stop layer is an etch stop layer of the second etch process step.

5. The FIR sensor device of claim 2 , wherein the first etch process step is an anisotropic etch process step, and the second etch process step is an isotropic etch process step.

6. The FIR sensor device of claim 2 , wherein the second etch process step is a wet etch process step which employs an etch solution including tetramethylammonium hydroxide (TMAH) solution and/or potassium hydroxide (KOH) solution.

7. The FIR sensor device of claim 1 , wherein the FIR sensor device includes a thermopile sensor device.

8. A manufacturing method of a far infrared (FIR) sensor device, comprising:
forming a sensor region in a substrate, wherein the sensor region is configured to operably sense a far infrared signal;
forming a sensor dielectric layer on the sensor region with a thickness;
depositing a sacrificial metal layer on the sensor dielectric layer;
forming an intermediate dielectric layer on the sacrificial metal layer;
etching the intermediate dielectric layer by a first etch process step, wherein an etch rate of the first etch process step etching the intermediate dielectric layer is higher than an etch rate of the first etch process step etching the sacrificial metal layer, wherein the sacrificial metal layer is an etch stop layer of the first etch process step; and
etching the sacrificial metal layer by a second etch process step.

9. The manufacturing method of claim 8 , wherein a periphery circuit is formed on the substrate, wherein the periphery circuit at includes least one metal oxide semiconductor (MOS) device and a plurality of metal layers, and wherein one of the plurality of metal layers and the sacrificial metal layer are formed by a same metal deposition process step.

10. The manufacturing method of claim 8 , further comprising:
depositing a stop layer between the sensor dielectric layer and the sacrificial metal layer;
wherein an etch rate of the second etch process step etching the sacrificial metal layer is higher than an etch rate of the second etch process step etching the stop layer, wherein the stop layer is an etch stop layer of the second etch process step.

11. The manufacturing method of claim 8 , wherein the first etch process step is an anisotropic etch process step, and the second etch process step is an isotropic etch process step.

12. The manufacturing method of claim 8 , wherein the second etch process step is a wet etch process step which employs an etch solution including tetramethylammonium hydroxide (TMAH) solution and/or potassium hydroxide (KOH) solution.

13. The manufacturing method of claim 8 , wherein the FIR sensor device includes a thermopile sensor device.

14. A determination method of a thickness of a sensor dielectric layer of a far infrared (FIR) sensor device, wherein the FIR sensor device is formed on a substrate, and includes: a sensor region, which is configured to operably sense a far infrared signal; and a sensor dielectric layer, which is formed on the sensor region with a thickness; the determination method comprising:
depositing a sacrificial metal layer on the sensor dielectric layer;
forming an intermediate dielectric layer on the sacrificial metal layer;
etching the intermediate dielectric layer by a first etch process step, wherein an etch rate of the first etch process step etching the intermediate dielectric layer is higher than an etch rate of the first etch process step etching the sacrificial metal layer, wherein the sacrificial metal layer is an etch stop layer of the first etch process step; and
etching the sacrificial metal layer by a second etch process step.

15. The determination method of claim 14 , wherein a periphery circuit is formed on the substrate, wherein the periphery circuit at includes least one metal oxide semiconductor (MOS) device and a plurality of metal layers, and wherein one of the plurality of metal layers and the sacrificial metal layer are formed by a same metal deposition process step.

16. The determination method of claim 14 further comprising:
depositing a stop layer between the sensor dielectric layer and the sacrificial metal layer;
wherein an etch rate of the second etch process step etching the sacrificial metal layer is higher than an etch rate of the second etch process step etching the stop layer, wherein the stop layer is an etch stop layer of the second etch process step.

17. The determination method of claim 14 , wherein the first etch process step is an anisotropic etch process step, and the second etch process step is an isotropic etch process step.

18. The determination method of claim 14 , wherein the second etch process step is a wet etch process step which employs an etch solution including tetramethylammonium hydroxide (TMAH) solution and/or potassium hydroxide (KOH) solution.

19. The determination method of claim 14 , wherein the FIR sensor device includes a thermopile sensor device.

Assignees

• Pixart Imaging Inc

Inventors

• Tsai Ming-Han
• Hu Chih-Fan

Classifications

• H10D84/80 Primary

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs (H10D84/40 takes precedence) · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F30/21

  the devices being sensitive to infrared, visible or ultraviolet radiation · CPC title

• G01J5/12

  using thermoelectric elements, e.g. thermocouples · CPC title

• G01J5/024 Primary

  Special manufacturing steps or sacrificial layers or layer structures · CPC title