Semiconductor device with buried bit line and preparation method thereof

Patent metadata

Field	Value
Publication number	US-12120868-B2
Application number	US-202117599393-A
Country	US
Kind code	B2
Filing date	Jun 29, 2021
Priority date	Nov 12, 2020
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A semiconductor device with a buried bit line and a preparation method thereof are provided. The preparation method of a semiconductor device with a buried bit line includes: providing a substrate; forming bit line trenches; forming a bit line structure in the bit line trench; and forming word line structures in the substrate. The semiconductor device with a buried bit line includes a substrate, bit line trenches, a bit line structure, and word line structures.

First claim

The invention claimed is:

1. A preparation method of a semiconductor device with a buried bit line, comprising:
providing a substrate, and forming, in the substrate, a plurality of active regions defined by an isolation structure, wherein each of the active regions extends along a first direction;
forming bit line trenches, wherein each of the bit line trenches extends along a second direction, each of the bit line trenches sequentially passes through the active region and the isolation structure in an S-shaped trend, and the second direction forms an acute angle with the first direction;
forming a bit line structure in each of the bit line trenches, wherein the bit line structure comprises a bit line formed at a bottom of each of the bit line trenches and an isolation layer covering the bit line; and
forming word line structures in the substrate, wherein each of the word line structures extends along a third direction and sequentially passes through the active region and the isolation structure, the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structure, and in the active region, the bit line and the word line structure are disposed at intervals;
wherein a depth of each of the word line structures passing through the isolation structure is less than a depth of each of the word line structures passing through the active region.

2. The preparation method of the semiconductor device with the buried bit line according to claim 1 , wherein
the forming, in the substrate, a plurality of active regions defined by an isolation structure comprises:
forming the isolation structure in the substrate, wherein the substrate is divided into a plurality of primary regions by the isolation structure; and
doping each of the primary regions to form each of the active regions.

3. The preparation method of the semiconductor device with the buried bit line according to claim 2 , before the doping each of the primary regions to form each of the active regions, further comprising:
forming bit-line primary trenches in the substrate, wherein each of the bit-line primary trenches extends along the second direction, each of the bit-line primary trenches sequentially passes through the active region and the isolation structure, and a trend of the bit-line primary trench is the same as a trend of the bit line trench; and
doping each of the primary regions to form each of the active regions, the active region comprises a first doping region and a second doping region with different heights, wherein the first doping region is a region below the bit-line primary trench, and the second doping region is a region on a side of the bit-line primary trench.

4. The preparation method of the semiconductor device with the buried bit line according to claim 3 , wherein
the forming bit line trenches, each of the bit line trenches is formed at a bottom of each of the bit-line primary trenches, and a width of the bit line trench is less than a width of the bit-line primary trench.

5. The preparation method of the semiconductor device with the buried bit line according to claim 4 , wherein
the bit line is formed at the bottom of the bit line trench and the isolation layer covering the bit line is formed, the isolation layer further fills the bit-line primary trench.

6. The preparation method of the semiconductor device with the buried bit line according to claim 1 , before the forming word line structures in the substrate, further comprising
thinning each of the active regions from an upper surface of the active region.

7. The preparation method of the semiconductor device with the buried bit line according to claim 1 , after the forming word line structures in the substrate, further comprising
forming an insulation layer on a surface of the substrate.

8. The preparation method of the semiconductor device with the buried bit line according to claim 7 , after the forming an insulation layer on a surface of the substrate, further comprising:
forming capacitive contact holes, wherein each of the capacitive contact holes runs through the insulation layer to the active region; and
forming a conductive plug in the capacitive contact hole, wherein the conductive plug is in contact with the active region.

9. The preparation method of the semiconductor device with the buried bit line according to claim 3 , wherein
a height of the first doping region is less than a height of the second doping region.

10. A semiconductor device with a buried bit line, comprising:
a substrate, wherein the substrate is provided with a plurality of active regions defined by an isolation structure, and each of the active regions extends along a first direction;
bit line trenches, extending along a second direction, wherein each of the bit line trenches sequentially passes through the active region and the isolation structure in an S-shaped trend, and the second direction forms an acute angle with the first direction;
a bit line structure, comprising a bit line and an isolation layer, wherein the bit line is formed in the each of bit line trenches, and the isolation layer covers the bit line and fills the bit line trenches; and
word line structures, extending along a third direction, and sequentially passing through the active region and the isolation structure, wherein the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structures, and in the active region, the bit line and the word line structure are disposed at intervals;
wherein a depth of each of the word line structures passing through the isolation structure is less than a depth of each of the word line structures passing through the active region.

11. The semiconductor device with the buried bit line according to claim 10 , wherein
the substrate further comprises bit-line primary trenches, each of the bit-line primary trenches extends along the second direction, each of the bit-line primary trenches sequentially passes through the active region and the isolation structure, a trend of the bit-line primary trench is the same as a trend of the bit line trench, the active region comprises a first doping region located below the bit-line primary trench and a second doping region located on a side of the bit-line primary trench, the bit line trench is located in the first doping region, and the isolation layer further fills the bit-line primary trench.

12. A semiconductor device with a buried bit line, comprising:
a substrate, wherein the substrate is provided with a plurality of active regions defined by an isolation structure, and each of the active regions extends along a first direction;
bit line trenches, extending along a second direction, wherein each of the bit line trenches sequentially passes through the active region and the isolation structure in an S-shaped trend, and the second direction forms an acute angle with the first direction:
a bit line structure, comprising a bit line and an isolation layer, wherein the bit line is formed in the each of bit line trenches, and the isolation layer covers the bit line and fills the bit line trenches; and
word line structures, extending along a third direction, and sequentially passing through the active region and the isolation structure, wherein the third direction is perpendicular to the second direction, in the isolation structure, the bit line is located below the word line structures, and in the active region, the bit line and the word line structure are disposed at intervals:
wherein
a width of each of the bit line trenches is less than a width of

Assignees

• Changxin Memory Tech Inc

Inventors

• Li Ran
• Jin Xing
• Cheng Ming

Classifications

• H10B12/488

  Word lines · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/30

  DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells · CPC title

• H10B12/482 Primary

  Bit lines · CPC title