Power semiconductor device having vertically parallel p-n layers formed in an active region under transistor cells and under a non-depletable extension zone formed in the edge region

Patent metadata

Field	Value
Publication number	US-12119376-B2
Application number	US-201916587631-A
Country	US
Kind code	B2
Filing date	Sep 30, 2019
Priority date	May 14, 2014
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

First claim

What is claimed is:

1. A switched-mode power supply comprising a power semiconductor device that comprises:
a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones,
wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device,
wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and
wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

2. The switched-mode power supply of claim 1 , wherein the drift zone comprises a compensation structure, wherein the compensation structure includes first zones of a first conductivity type and second zones of a second, opposite conductivity type, the first and second zones alternately arranged along a horizontal direction orthogonal to a vertical direction, the vertical direction defined by a direct connection line between one of the transistor cells and the drain layer.

3. The switched-mode power supply of claim 2 , wherein a vertical dopant profile of the first zones includes local maxima between local minima and the local maxima exceed the neighboring local minima by not more than 20%.

4. The switched-mode power supply of claim 2 , wherein the transistor cells are arranged in an active area of the semiconductor body, and an edge area between the active area and a lateral surface of the semiconductor body is devoid of transistor cells.

5. The switched-mode power supply of claim 4 , wherein the edge area comprises at least one of an intrinsic portion, an insulator trench or pairs of superposed first and second zones.

6. The switched-mode power supply of claim 4 , wherein the edge area in total comprises less first and second zones per volume unit than the active area or is devoid of the first and second zones.

7. The switched-mode power supply of claim 4 , further comprising:
an interlayer dielectric structure adjoining a first surface of the semiconductor body and separating, in the edge area, a gate construction from the semiconductor body; and
a non-depletable extension zone in the semiconductor body in a vertical projection of at least a portion of the gate construction, wherein the non-depletable extension zone is of a conductivity type of body zones of the transistor cells and electrically connected to one of the body zones.

8. The switched-mode power supply of claim 7 , wherein
the non-depletable extension zone extends over at least 40% of a vertical projection of the gate construction.

9. The switched-mode power supply of claim 7 , wherein the non-depletable extension zone is electrically connected to a load electrode.

10. The switched-mode power supply of claim 7 , wherein in the non-depletable extension zone an effective dopant dose is greater than 2.5E12 cm −2 .

11. The switched-mode power supply of claim 1 , wherein an areal on state resistance of the semiconductor device is less than 1.5 Ohm*mm 2 and a breakdown voltage is greater than 600 V.

12. A semiconductor device, comprising:
a semiconductor body comprising:
a drain layer extending to a rear surface of the semiconductor body;
a drift zone disposed over the drain layer and having a lower dopant concentration than the drain layer;
an active area comprising one or more transistor cells, each of the transistor cells comprising source zones disposed over the drift zone and extending to a main surface of the semiconductor body that is opposite from the rear surface, and a gate configured to control a conductive channel between the source zones and the drain layer;
wherein the semiconductor device exhibits a first output charge gradient when a voltage between the drain layer and the source zones increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device,
wherein the semiconductor device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and
wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.

13. The semiconductor device of claim 12 , wherein the drift zone comprises a compensation structure, wherein the compensation structure includes first zones of a first conductivity type and second zones of a second, opposite conductivity type, the first and second zones alternately arranged along a horizontal direction that is parallel to the main and rear surfaces, and wherein a vertical dopant profile of the first zones includes local maxima between local minima and the local maxima exceed the neighboring local minima by not more than 20%.

14. The semiconductor device of claim 13 , wherein the semiconductor body further comprises an edge area that is devoid of the transistor cells that separates the active area from a lateral surface of the semiconductor body, the lateral surface extending between the main and rear surfaces, and wherein the edge area comprises at least one of an intrinsic portion, an insulator trench or pairs of superposed ones of the first and second zones.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Willmeroth Armin
• Hirler Franz
• Fischer Bjoern
• Weyers Joachim

Classifications

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/519

  characterised by their top-view geometrical layouts · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title