Method for manufacturing a semiconductor device

Patent metadata

Field	Value
Publication number	US-9418851-B2
Application number	US-201615068749-A
Country	US
Kind code	B2
Filing date	Mar 14, 2016
Priority date	Dec 31, 2013
Publication date	Aug 16, 2016
Grant date	Aug 16, 2016

Abstract

A wafer includes a semiconductor layer having a concentration of n-dopants. A first mask is formed on the wafer and has first openings in an active area of a semiconductor device and at least one second opening in a peripheral area of the device. The first openings define first zones in the semiconductor layer and each second opening defines a second zone in the layer. Donor ions are implanted through the first mask into the first and second zones. The first mask is replaced by a second mask which has third openings in the active area and at least one fourth opening in the peripheral area. Each fourth opening defines a fourth zone in the semiconductor layer which at least partially overlaps with the second zone. The third openings define third zones in the semiconductor layer. Acceptor ions are implanted through the second mask into the third and fourth zones.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, the method comprising:
providing a wafer having an upper side and comprising a semiconductor layer having a first concentration of n-dopants;
forming a first mask on the upper side, the first mask comprising, in a cross-section substantially orthogonal to the upper side, first openings in an active area of a semiconductor device and at least one second opening in a peripheral area of the semiconductor device, the first openings defining first zones in the semiconductor layer and the at least one second opening defining a second zone in the semiconductor layer;
implanting donor ions of a first maximum energy through the first mask into the first zones and the second zone;
replacing the first mask by a second mask comprising, in the cross-section, third openings in the active area of the semiconductor device and at least one fourth opening in the peripheral area of the semiconductor device, the at least one fourth opening defining a fourth zone in the semiconductor layer which at least partially overlaps with the second zone, the third openings defining third zones in the semiconductor layer; and
implanting acceptor ions of a second maximum energy through the second mask into the third zones and the fourth zone.

2. The method of claim 1 , wherein a layout of the first mask and a layout of the second mask are chosen such that the first zones, the second zones, the third zones and the fourth zones comprise respective substantially strip-shaped portions which are substantially parallel to each other when seen from above.

3. The method of claim 1 , wherein a layout of the first mask and the second mask is chosen such that at least one of the first zones and the third zones merges with at least one of the second zone.

4. The method of claim 1 , wherein a layout of the first mask and the second mask is chosen such that the at least one fourth zone substantially corresponds to the at least one second zone when seen from above, and/or wherein the at least one fourth zone is arranged within the at least one second zone when seen from above.

5. The method of claim 1 , further comprising:
implanting donor ions of an energy different to the first maximum energy through the first mask into the first zones and the second zone.

6. The method of claim 1 , further comprising:
implanting acceptor ions of an energy different to the second maximum energy through the second mask into the third zones and the fourth zone.

7. The method of claim 1 , further comprising:
epitaxial depositing of a further semiconductor layer having the first concentration of n-dopants.

8. The method of claim 1 , further comprising:
carrying out at least one temperature step to activate donor ions implanted in the first zones and the second zone and to activate acceptor ions implanted in the third zones and the fourth zone.

9. The method of claim 1 , further comprising:
forming a source metallization in ohmic contact with p-type semiconductor regions formed in the third zones.

10. The method of claim 1 , further comprising:
forming a drain metallization in ohmic contact with n-type semiconductor regions formed in the first zones.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Hirler Franz
• Knoefler Roman
• Mauder Anton
• Weber Hans
• Weyers Joachim

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10D62/054

  by high energy implantations in bulk semiconductor bodies, e.g. forming pillars · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title