Semiconductor structure having a semiconductor substrate and an isolation component

Patent metadata

Field	Value
Publication number	US-12119343-B2
Application number	US-202217886161-A
Country	US
Kind code	B2
Filing date	Aug 11, 2022
Priority date	Aug 17, 2018
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a) a P-type semiconductor substrate having a first region, a second region comprising an N-type second well region, and an isolation region disposed between the first region and the second region;
b) an isolation component located in the isolation region;
c) wherein the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region, and the electric potential connected to the isolation component is not higher than the electric potential of the semiconductor substrate;
d) wherein the isolation component comprises a trench and a P-type contact region located on a surface of the isolation region and in contact with the trench, and wherein the isolation component is without an N-type doped region, wherein a depth of the P-type contact region is less than a depth of the trench; and
e) wherein a second N-type MOSFET is disposed in the second well region and a first N-type MOSFET is disposed in the first region, wherein a parasitic PNP transistor is formed by a P-type body region of the second N-type MOSFET, the second well region, and the semiconductor substrate, and wherein a parasitic NPN transistor is formed by the second well region, the semiconductor substrate, and an N-type region of the first N-type MOSFET.

2. The semiconductor structure according to claim 1 , wherein:
a) the first carrier is electron carrier, and the second carrier is hole carrier; and
b) the portion of the isolation component adjacent to the semiconductor substrate is P-type doped or a metal-containing conductive material.

3. The semiconductor structure according to claim 2 , wherein:
a) the N-type region is adjacent to the semiconductor substrate;
b) the second carriers flow from the PNP transistor toward the first region when the PNP transistor is turned on; and
c) the first carriers flow from the NPN transistor toward the second region when the NPN transistor is turned on.

4. The semiconductor structure according to claim 3 , wherein:
a) the first region comprises an N-type first well region;
b) the first N-type MOSFET is disposed in the first well region; and
c) the N-type region is the first well region.

5. The semiconductor structure according to claim 3 , wherein:
a) a drain electrode of the second N-type MOSFET is connected to a first electric potential;
b) a source electrode of the second N-type MOSFET is coupled to a drain electrode of the first N-type MOSFET;
c) a drain electrode of the first N-type MOSFET is connected to a second electric potential; and
d) the first electric potential is greater than the second electric potential.

6. The semiconductor structure according to claim 4 , wherein:
a) the second N-type MOSFET is configured as a high-voltage side transistor of a second half-bridge circuit;
b) the first N-type MOSFET is configured as a low-voltage side transistor of a first half-bridge circuit; and
c) a source electrode of the second N-type MOSFET is coupled to a drain electrode of the first N-type MOSFET through an inductive element.

7. The semiconductor structure according to claim 3 , wherein a source region of the second N-type MOSFET is located in the P-type body region.

8. The semiconductor structure according to claim 3 , wherein a depth of the isolation component in the semiconductor substrate is greater than a depth of the second well region in the semiconductor substrate along a thickness direction of the semiconductor substrate.

9. The semiconductor structure according to claim 2 , wherein the isolation component comprises:
a) the trench extending from the surface of the isolation region toward the inside of the semiconductor substrate along a thickness direction of the semiconductor substrate; and
b) a P-type doped polysilicon or a metal-containing conductive material filled in the b) trench.

10. A driver chip, comprising the semiconductor structure of claim 3 and an inductive element, wherein:
a) the second N-type MOSFET is a high voltage side transistor of a second half-bridge circuit in the driving chip;
b) the first N-type MOSFET is a low voltage side transistor of a first half-bridge circuit in the driving chip; and
c) the source electrode of the second N-type MOSFET is coupled to a drain c) electrode of the first N-type MOSFET through the inductive element.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Du Yicheng
• Wang Meng
• Yu Hui

Classifications

• H10W10/031 Primary

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10W10/0148

  comprising introducing impurities in side walls or bottom walls of trenches, e.g. for forming channel stoppers · CPC title