Hermetic package for high CTE mismatch

Patent metadata

Field	Value
Publication number	US-12119281-B2
Application number	US-202117394093-A
Country	US
Kind code	B2
Filing date	Aug 4, 2021
Priority date	Aug 4, 2020
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

The present disclosure relates to a hermetic package capable of handling a high coefficient of thermal expansion (CTE) mismatch configuration. The disclosed hermetic package includes a metal base and multiple segments that are discrete from each other. Herein, a gap exists between every two adjacent ceramic wall segments and is sealed with a connecting material. The ceramic wall segments with the connecting material form a ring wall, where the gap between every two adjacent ceramic wall segments is located at a corner of the ring wall. The metal base is either surrounded by the ring wall or underneath the ring wall.

First claim

What is claimed is:

1. A package comprising:
a metal base having a top surface; and
multiple ceramic wall segments horizontally discrete from each other, wherein:
a gap exists between every two horizontally adjacent ceramic wall segments and is sealed with a connecting material that is a solder or a brazing alloy, such that the connecting material is located at least between the every two horizontally adjacent ceramic wall segments;
the ceramic wall segments with the connecting material form a ring wall, wherein the gap between the every two horizontally adjacent ceramic wall segments is located at a corner of the ring wall; and
the ring wall is attached to the top surface of the metal base, such that a first portion of the top surface of the metal base is exposed through the ring wall.

2. The package of claim 1 wherein a bottom surface of each ceramic wall segment is metalized and connected to the top surface of the metal base via the connecting material.

3. The package of claim 1 wherein the gap that exists between the every two horizontally adjacent ceramic wall segments is between 0-50 thousandth of an inch.

4. The package of claim 1 wherein the metal base has a coefficient of thermal expansion (CTE) >11 μm/m·K, and each ceramic wall segment has a CTE <9 μm/m·K.

5. The package of claim 4 wherein:
the metal base is formed of copper, copper molybdenum, copper tungsten, a layered stack of copper and tungsten, or a layered stack of copper and moly; and
each ceramic wall segment is formed of alumina.

6. The package of claim 1 wherein the number of the ceramic wall segments is four, and the every two horizontally adjacent ceramic wall segments are orthogonal.

7. The package of claim 6 wherein the four ceramic wall segments are identical, and the ring wall is a square ring wall.

8. The package of claim 6 wherein:
each ceramic wall segment has two end sides, and a surface of each end side is metalized; and
each gap is formed between the metalized surfaces of two facing end sides of the every two horizontally adjacent ceramic wall segments.

9. The package of claim 8 further comprising a plurality of input-side leads and a plurality of output-side leads, wherein the plurality of input-side leads and the plurality of output-side leads are electrically connected to two of the four ceramic wall segments respectively.

10. The package of claim 9 wherein:
each ceramic wall segment includes a top region and a bottom region underneath the top region; and
the bottom region is larger than the top region, wherein a top surface of the bottom region is partially exposed.

11. The package of claim 10 wherein:
the top region is located above a middle portion of the top surface of the bottom region, such that an inner portion and an outer portion of the top surface of the bottom region are exposed, and each ceramic wall segment has a castellation internal side and a castellation external side;
the plurality of input-side leads is formed on the exposed outer portion of the top surface of the bottom region of a corresponding ceramic wall segment and extends outward from the corresponding ceramic wall segment; and
the plurality of output-side leads is formed on the exposed outer portion of the top surface of the bottom region of another corresponding ceramic wall segment and extends outward from the other corresponding ceramic wall segment.

12. The package of claim 10 further comprising a ring structure over a top surface of the top region of each ceramic wall segment.

13. The package of claim 12 wherein:
the ring structure is formed of a copper alloy or an iron alloy; and
the top surface of the top region of each ceramic wall segment is metalized.

14. The package of claim 13 further comprising a lid placed over the ring structure, wherein the lid is formed of a copper alloy or an iron alloy, and the ring structure is configured to provide a consistent sealing surface to the lid.

15. The package of claim 14 wherein the metal base, the ring wall, the ring structure, the lid, and the connecting material form a hermetic cavity, which is capable of accommodating at least one semiconductor die, wherein the at least one semiconductor die is mounted on the first portion of the top surface of the metal base and located within the hermetic cavity.

16. The package of claim 10 wherein:
the top region has a trapezoidal shape in a horizontal plane, and the bottom region has a trapezoidal shape in a horizontal plane; and
end sides of the top region are aligned with end sides of the bottom region, respectively, and the surface of each end side of each ceramic wall segment is flat.

17. The package of claim 10 further comprising a lid formed of a ceramic material, wherein the lid is placed over a top surface of the top region of each ceramic wall segment.

18. The package of claim 17 wherein:
each ceramic wall segment is formed of alumina, and the top surface of the top region of each ceramic wall segment is metalized;
a peripheral portion of a bottom surface of the lid is metalized; and
the metalized peripheral portion of the bottom surface of the lid is connected to the metalized top surface of the top region of each ceramic wall segment via the connecting material.

19. The package of claim 17 wherein the metal base, the ring wall, the lid, and the connecting material form a hermetic cavity, which is capable of accommodating at least one semiconductor die, wherein the at least one semiconductor die is mounted on the first portion of the top surface of the metal base and located within the hermetic cavity.

Assignees

• Qorvo Us Inc

Inventors

• Murdock Dylan

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W76/17

  characterised by their materials · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/682

  comprising holes having chips therein · CPC title