Method for producing a connection structure and semiconductor device

Patent metadata

Field	Value
Publication number	US-12119236-B2
Application number	US-202017442624-A
Country	US
Kind code	B2
Filing date	Mar 20, 2020
Priority date	Mar 26, 2019
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

A method of manufacturing a connection structure may include forming an opening in a first main surface of a first substrate, forming a galvanic seed layer over a first main surface of a carrier substrate, and connecting the first main surface of the first substrate to the first main surface of the carrier substrate, such that the galvanic seed layer is arranged between the first main surface of the first substrate and the first main surface of the carrier substrate. The method may further include galvanically forming a conductive material over the galvanic seed layer.

First claim

The invention claimed is:

1. A method of manufacturing a connection structure, wherein the method comprises:
forming an opening in a first main surface of a first substrate;
forming a galvanic seed layer over a first main surface of a carrier substrate;
forming a first insulating connection layer over the first main surface of the first substrate and over sidewalls of the opening;
applying a second connection layer over the galvanic seed layer,
connecting the first substrate to the carrier substrate, such that the galvanic seed layer is arranged between the first main surface of the first substrate and the first main surface of the carrier substrate and the first main surface of the first substrate is arranged between a second main surface of the first substrate and the carrier substrate;
wherein the galvanic seed layer is formed over the first main surface of the carrier substrate before the first substrate is connected to the carrier substrate;
thinning the first substrate such that the opening in the first substrate is opened on the second main surface of the first substrate facing away from the carrier substrate; removing the second connection layer from the surface of the opening facing the carrier substrate after the first substrate and the carrier substrate have been joined together such that part of the galvanic seed layer is exposed,
galvanically forming a conductive material over the galvanic seed layer; and
removing the carrier substrate after the second main surface of the first substrate has been connected to the second semiconductor substrate, wherein after removing the carrier substrate portions of the second connection layer are arranged over portions of the first substrate adjacent to the conductive material.

2. The method according to claim 1 , further comprising forming an insulation layer over sidewalls of the opening in the first substrate.

3. The method according to claim 1 , wherein the conductive material completely fills the opening in the first substrate.

4. The method according to claim 1 , wherein the opening in the first substrate has a width greater than 20 μm.

5. The method according to claim 1 , wherein a depth of the opening in the first substrate is greater than 50 μm.

6. The method according to claim 1 , further comprising forming a separating layer over the carrier substrate, wherein the separating layer is arranged between the galvanic seed layer and the first main surface of the carrier substrate.

7. The method according to claim 1 , further comprising connecting the second main surface of the first substrate to a second semiconductor substrate within which a functional portion is arranged such that the functional portion is electrically connected to the conductive material.

8. A semiconductor device obtained by the method according to claim 1 .

9. The method according to claim 1 , wherein a material of the first insulating connection layer is identical with the material of the second connection layer.

10. The method according to claim 6 , wherein removing the carrier substrate comprises detaching the carrier substrate from the separating layer.

Assignees

• Osram Opto Semiconductors Gmbh

Inventors

• Rudolph Andreas
• Baur Teresa
• Klemp Christoph

Classifications

• H10W70/635

  Through-vias · CPC title

• H10W70/611

  for connecting multiple chips together · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title