Spacer film scheme for polarization improvement

Patent metadata

Field	Value
Publication number	US-12119035-B2
Application number	US-202318150281-A
Country	US
Kind code	B2
Filing date	Jan 5, 2023
Priority date	Jul 29, 2022
Publication date	Oct 15, 2024
Grant date	Oct 15, 2024

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode disposed within a dielectric structure over a substrate. A ferroelectric data storage structure is disposed over the lower electrode and an upper electrode is disposed over the ferroelectric data storage structure. One or more stressed sidewall spacers are arranged on opposing sides of the upper electrode. The ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

First claim

What is claimed is:

1. An integrated chip, comprising:
a lower electrode disposed within a dielectric structure over a substrate;
a ferroelectric data storage structure disposed over the lower electrode;
an upper electrode disposed over the ferroelectric data storage structure; and
one or more stressed sidewall spacers arranged on opposing sides of the upper electrode, wherein the ferroelectric data storage structure has an orthorhombic phase concentration that varies from directly below the one or more stressed sidewall spacers to laterally outside of the one or more stressed sidewall spacers.

2. The integrated chip of claim 1 , wherein the one or more stressed sidewall spacers have a tensile stress that is in a range of between approximately 100 MPa (megapascals) and approximately 900 MPa.

3. The integrated chip of claim 1 , wherein the one or more stressed sidewall spacers comprise silicon nitride or silicon carbon nitride.

4. The integrated chip of claim 1 , wherein the ferroelectric data storage structure has a maximum orthorhombic phase of greater than 75% directly below the one or more stressed sidewall spacers.

5. The integrated chip of claim 1 , wherein the ferroelectric data storage structure comprises a polar orthorhombic phase and a non-polar orthorhombic phase, a concentration of the polar orthorhombic phase being greater than a concentration of the non-polar orthorhombic phase directly below the one or more stressed sidewall spacers.

6. The integrated chip of claim 1 , wherein the orthorhombic phase concentration of the ferroelectric data storage structure is larger directly below the one or more stressed sidewall spacers than directly below the upper electrode.

7. The integrated chip of claim 1 , wherein the one or more stressed sidewall spacers are disposed over a topmost point of the ferroelectric data storage structure.

8. The integrated chip of claim 1 , wherein the one or more stressed sidewall spacers extend to within one or more recesses in an upper surface of the ferroelectric data storage structure.

9. An integrated chip, comprising:
one or more lower interconnects arranged within a dielectric structure over a substrate;
a lower electrode disposed over the one or more lower interconnects;
a ferroelectric data storage structure disposed on the lower electrode;
an upper electrode disposed on the ferroelectric data storage structure;
one or more stressed sidewall spacers arranged on opposing sides of the upper electrode, wherein the one or more stressed sidewall spacers comprise a tensile stress; and
wherein the ferroelectric data storage structure has a central region directly below the upper electrode and one or more peripheral regions directly below the one or more stressed sidewall spacers, the one or more peripheral regions having a first polar orthorhombic phase concentration that is higher than a second polar orthorhombic phase concentration within the central region.

10. The integrated chip of claim 9 , wherein the first polar orthorhombic phase concentration is more than 30% larger than the second polar orthorhombic phase concentration.

11. The integrated chip of claim 9 , wherein the first polar orthorhombic phase concentration within the one or more peripheral regions is higher than a second non-polar orthorhombic phase concentration within the one or more peripheral regions.

12. The integrated chip of claim 9 , wherein the first polar orthorhombic phase concentration is greater than approximately 75% and the second polar orthorhombic phase concentration is greater than approximately 40%.

13. A method of forming an integrated chip (IC), comprising:
forming one or more lower interconnects within a lower dielectric structure formed over a substrate;
forming a lower electrode layer over the one or more lower interconnects;
forming a ferroelectric data storage layer over the lower electrode layer;
forming an upper electrode over the ferroelectric data storage layer;
forming one or more stressed sidewall spacers along opposing sides of the upper electrode; and
performing an anneal process after forming the one or more stressed sidewall spacers to increase an orthorhombic phase concentration within parts of the ferroelectric data storage layer.

14. The method of claim 13 , further comprising:
patterning the lower electrode layer and the ferroelectric data storage layer after performing the anneal process to form a lower electrode that is separated from the upper electrode by a ferroelectric data storage structure.

15. The method of claim 13 , wherein the anneal process increases the orthorhombic phase concentration within the parts of the ferroelectric data storage layer by between approximately 100% and approximately 1000%.

16. The method of claim 13 , wherein the anneal process increases a polar orthorhombic phase concentration within the parts the ferroelectric data storage layer by a first amount that is larger than a second amount by which a non-polar orthorhombic phase concentration is increased within the parts of the ferroelectric data storage layer.

17. The method of claim 13 , wherein the anneal process increases the orthorhombic phase concentration within a central region of the ferroelectric data storage layer by a first amount and further increases the orthorhombic phase concentration within one or more peripheral regions of the ferroelectric data storage layer by a second amount that is larger than the first amount.

18. The method of claim 13 ,
wherein the orthorhombic phase concentration within a central region of the ferroelectric data storage layer is greater than the orthorhombic phase concentration within one or more peripheral regions of the ferroelectric data storage layer prior to performing the anneal process; and
wherein the orthorhombic phase concentration within the central region of the ferroelectric data storage layer is smaller than the orthorhombic phase concentration within the one or more peripheral regions of the ferroelectric data storage layer after performing the anneal process.

19. The method of claim 13 , wherein the ferroelectric data storage layer has a central region laterally surrounded by one or more peripheral regions, the orthorhombic phase concentration of the central region being smaller than the orthorhombic phase concentration of the one or more peripheral regions after performing the anneal process.

20. The method of claim 13 , wherein the ferroelectric data storage layer has a central region laterally surrounded by one or more peripheral regions, wherein performing the anneal process reduces a variation in the orthorhombic phase concentration between the central region and the one or more peripheral regions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Tzu-Yu
• Chang Yao-Wen

Classifications

• H10D64/671

  the conductor having lateral variation in doping or structure · CPC title

• H10D1/682

  having dielectrics comprising perovskite structures · CPC title

• H10B51/30

  characterised by the memory core region · CPC title

• G11C11/221

  using ferroelectric capacitors · CPC title

• H10B53/20

  characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title