Dual-stripline with crosstalk cancellation

Patent metadata

Field	Value
Publication number	US-12113265-B2
Application number	US-202117214111-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Mar 26, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

Electronic structures including a dual-stripline with crosstalk cancellation are described. In an example, a printed circuit board (PCB), a package substrate or a semiconductor die includes a dual-stripline structure. The dual-stripline structure includes a first region including a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line. The dual-stripline structure also includes a second region including the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line. The dual-stripline structure also includes a transition region between the first region and the second region. The first bottom line and the second bottom line cross in the transition region.

First claim

What is claimed is:

1. A printed circuit board (PCB) comprising a dual-stripline structure, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.

2. The PCB of claim 1 , wherein the first bottom line crosses over the second bottom line in the transition region using a first via and a second via, the first via raising the first bottom line from a plane of the second bottom line to a plane of the first top line and the second top line, and the second via lowering the first bottom line from the plane of the first top line and the second top line to the plane of the second bottom line.

3. The PCB of claim 2 , further comprising:
a ground plane above and beneath the dual-stripline structure, wherein the ground plane does not include a void beneath the transition region.

4. The PCB of claim 2 , wherein the first top line and the second top line are spaced further apart from one another in the transition region than in the first region and in the second region.

5. The PCB of claim 1 , wherein the first bottom line crosses below the second bottom line in the transition region using a first via and a second via, the first via lowering the first bottom line from a plane of the second bottom line to a lower plane, and the second via raising the first bottom line from the lower plane to the plane of the second bottom line.

6. The PCB of claim 5 , further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane includes a void beneath the transition region, and wherein the lower plane is in the void.

7. The PCB of claim 5 , wherein the first top line and the second top line are spaced a same distance from one another in the transition region as in the first region and in the second region.

8. A package substrate, comprising:
a plurality of alternating organic dielectric layers and metal layers; and
a dual-stripline structure in the plurality of alternating organic dielectric layers and metal layers, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.

9. The package substrate of claim 8 , wherein the first bottom line crosses over the second bottom line in the transition region using a first via and a second via, the first via raising the first bottom line from a plane of the second bottom line to a plane of the first top line and the second top line, and the second via lowering the first bottom line from the plane of the first top line and the second top line to the plane of the second bottom line.

10. The package substrate of claim 9 , further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane does not include a void beneath the transition region.

11. The package substrate of claim 9 , wherein the first top line and the second top line are spaced further apart from one another in the transition region than in the first region and in the second region.

12. The package substrate of claim 8 , wherein the first bottom line crosses below the second bottom line in the transition region using a first via and a second via, the first via lowering the first bottom line from a plane of the second bottom line to a lower plane, and the second via raising the first bottom line from the lower plane to the plane of the second bottom line.

13. The package substrate of claim 12 , further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane includes a void beneath the transition region, and wherein the lower plane is in the void.

14. The package substrate of claim 12 , wherein the first top line and the second top line are spaced a same distance from one another in the transition region as in the first region and in the second region.

15. A semiconductor die, comprising:
a semiconductor substrate;
a plurality of alternating dielectric layers and metal layers above the semiconductor substrate; and
a dual-stripline structure in the plurality of alternating dielectric layers and metal layers, the dual-stripline structure comprising:
a first region comprising a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line;
a second region comprising the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line; and
a transition region between the first region and the second region, wherein the first bottom line and the second bottom line cross in the transition region.

16. The semiconductor die of claim 15 , wherein the first bottom line crosses over the second bottom line in the transition region using a first via and a second via, the first via raising the first bottom line from a plane of the second bottom line to a plane of the first top line and the second top line, and the second via lowering the first bottom line from the plane of the first top line and the second top line to the plane of the second bottom line.

17. The semiconductor die of claim 16 , further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane does not include a void beneath the transition region.

18. The semiconductor die of claim 16 , wherein the first top line and the second top line are spaced further apart from one another in the transition region than in the first region and in the second region.

19. The semiconductor die of claim 15 , wherein the first bottom line crosses below the second bottom line in the transition region using a first via and a second via, the first via lowering the first bottom line from a plane of the second bottom line to a lower plane, and the second via raising the first bottom line from the lower plane to the plane of the second bottom line.

20. The semiconductor die of claim 19 , further comprising:
a ground plane beneath the dual-stripline structure, wherein the ground plane includes a void beneath the transition region, and wherein the lower plane is in the void.

21. The semiconductor die of claim 19 , wherein the first top line and the second top line are spaced a same distance from one another in the transition region as in the first region and in the second region.

Assignees

• Intel Corp

Inventors

• Sutono Albert
• Ye Xiaoning

Classifications

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title