Semiconductor device

Patent metadata

Field	Value
Publication number	US-12113059-B2
Application number	US-202218147935-A
Country	US
Kind code	B2
Filing date	Dec 29, 2022
Priority date	Jul 12, 2022
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

There is provided a semiconductor device and a method of manufacturing the same. The method comprises: depositing an epitaxial layer on a semiconductor substrate, wherein the semiconductor substrate is of a first conductivity type, and the epitaxial layer is of a second conductivity type that is opposite to the first conductivity type, wherein depositing the epitaxial layer comprises depositing a first epi-layer of a first doping concentration, a second epi-layer of a second doping concentration and a third epi-layer of a third doping concentration, and wherein the semiconductor substrate and the first epi-layer form a first P-N junction at their interface, and the second epi-layer is arranged between the first and third epi-layers and the second doping concentration is higher than each of the first doping concentration and the third doping concentration; and forming a doped region of the first conductivity type at a surface of the third epi-layer, such that the doped region 8 and the third epi-layer form a second P-N junction at their interface.

First claim

The invention claimed is:

1. A method of manufacturing a semiconductor device, comprising:
depositing an epitaxial layer on a semiconductor substrate, wherein the semiconductor substrate is of a first conductivity type N, and the epitaxial layer is of a second conductivity type P that is opposite to the first conductivity type, wherein depositing the epitaxial layer comprises depositing a first epi-layer of a first doping concentration, a second epi-layer of a second doping concentration and a third epi-layer of a third doping concentration, and wherein: the semiconductor substrate and the first epi-layer form a first P-N junction at their interface; the second epi-layer is arranged between the first and third epi-layers; and the second doping concentration is higher than each of the first doping concentration and the third doping concentration;
forming a first doped region of the first conductivity type N at a surface of the third epi-layer, such that the first doped region and the third epi-layer form a second P-N junction at their interface, wherein the semiconductor substrate, the epitaxial layer and the first doped region form a vertical bipolar junction transistor; and
forming a second doped region of the second conductivity type P at the surface of the third epi-layer, wherein the second doped region is surrounded by the first doped region, and a base of the vertical bipolar junction transistor is shorted to the second doped region.

2. The method of claim 1 , further comprising:
selectively etching the epitaxial layer and the semiconductor substrate to form a trench extending through the epitaxial layer into the semiconductor substrate.

3. The method of claim 2 , wherein the trench is of a tubular shape.

4. The method of claim 2 , further comprising filling the trench with an electrically insulating material.

5. The method of claim 2 , wherein the first doped region is separate from the trench without contacting the trench.

6. The method of claim 1 , further comprising: forming a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the semiconductor substrate.

7. The method of claim 1 , wherein the first doped region occupies less area than the third epi-layer along a plane that is parallel to a surface of the semiconductor substrate.

8. The method of claim 1 , wherein the second doped region, the epitaxial layer and the semiconductor substrate form a diode.

9. The method of claim 1 , wherein the second doped region has a higher doping concentration than the third epi-layer.

10. The method of claim 1 , wherein the semiconductor device is an electrostatic discharge (ESD) protection device.

11. A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type N;
an epitaxial layer arranged on the semiconductor substrate, wherein: the epitaxial layer is of a second conductivity type P that is opposite to the first conductivity type N; the epitaxial layer comprises a first epi-layer of a first doping concentration, a second epi-layer of a second doping concentration and a third epi-layer of a third doping concentration, with the semiconductor substrate and the first epi-layer forming a first P-N junction at their interface; and
the second epi-layer is arranged between the first and third epi-layers and the second doping concentration is higher than each of the first doping concentration and the third doping concentration;
a first doped region arranged at a surface of the third epi-layer, wherein the first doped region is of the first conductivity type N such that the first doped region and the third epi-layer form a second P-N junction at their interface, and wherein the semiconductor substrate, the epitaxial layer and the first doped region form a vertical bipolar junction transistor; and
a second doped region of the second conductivity type P arranged at the surface of the third epi-layer, wherein the second doped region is surrounded by the first doped region, and a base of the vertical bipolar junction transistor is shorted to the second doped region.

12. The semiconductor device of claim 11 , wherein the semiconductor device is an electrostatic discharge (ESD) protection device.

13. The semiconductor device of claim 11 , further comprising:
a trench extending through the epitaxial layer into the semiconductor substrate.

14. The semiconductor device of claim 13 , wherein the trench is of a tubular shape.

15. The semiconductor device of claim 13 , wherein the trench is filled with an electrically insulating material.

16. The semiconductor device of claim 13 , wherein the first doped region is separate from the trench without contacting the trench.

17. The semiconductor device of claim 13 , wherein the semiconductor device is an electrostatic discharge (ESD) protection device.

18. The semiconductor device of claim 11 , further comprising:
a first electrode electrically connected to the first doped region and the second doped region; and
a second electrode electrically connected to the semiconductor substrate.

19. The semiconductor device of claim 11 , wherein the second doped region, the epitaxial layer and the semiconductor substrate form a diode.

20. The semiconductor device of claim 11 , wherein the second doped region has a higher doping concentration than the third epi-layer.

Assignees

• Diodes Inc

Inventors

• Fogarty Cahir Michael
• Badcock Stephen Geoffrey

Classifications

• H10D89/60

  Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] · CPC title

• H10D8/422

  PN diodes having the PN junctions in mesas · CPC title

• H10D8/041

  of multilayer diodes · CPC title

• H10D8/021

  of breakdown diodes · CPC title

• H10D62/60

  Impurity distributions or concentrations · CPC title