Lead adapters for semiconductor package

Patent metadata

Field	Value
Publication number	US-12113000-B2
Application number	US-202117540673-A
Country	US
Kind code	B2
Filing date	Dec 2, 2021
Priority date	Dec 2, 2021
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

First claim

The invention claimed is:

1. A semiconductor package comprising:
a first semiconductor die;
an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die;
a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die; and
a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die,
wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

2. The semiconductor package of claim 1 , wherein the signal lead comprises a first outer face that extends towards the outer end of the signal lead, wherein lead adapter retention feature comprises an engagement surface that is spaced apart from the outer end of the signal lead and forms an angled edge with the first outer face.

3. The semiconductor package of claim 2 , wherein the engagement surface extends from a wider part of the signal lead to a narrower part of the signal lead, and wherein the wider part of the signal lead is arranged between the outer end of the signal lead and the lead adapter retention feature.

4. The semiconductor package of claim 3 , wherein the first outer face is an outer surface of the narrower part of the signal lead, and wherein the engagement surface forms a step-shaped transition between the narrower part of the signal lead and the wider part of the signal lead.

5. The semiconductor package of claim 4 , wherein the wider part of the signal lead is a cylindrically shaped end structure that laterally extends past the narrower part of the signal lead in every direction.

6. The semiconductor package of claim 4 , wherein the wider part of the signal lead is a winged end structure that projects away from the narrower part of the signal lead in two opposing directions.

7. The semiconductor package of claim 3 , wherein the first outer face is an outer surface of the wider part of the signal lead, and wherein the lead adapter retention feature comprises a notch in the wider part of the signal lead, and wherein the engagement surface is an interior surface of the notch.

8. The semiconductor package of claim 7 , wherein the angled edge of the engagement surface is substantially perpendicular with the first outer face, and wherein the notch further comprises a second interior surface that forms an oblique angle with the first outer face and intersects with the engagement surface at a nadir of the notch.

9. The semiconductor package of claim 7 , and wherein the notch further comprises a second interior surface that intersects with the engagement surface at a nadir of the notch, and wherein the engagement surface and the second interior surface are each form an oblique angle with the first outer face.

10. The semiconductor package of claim 1 , wherein the signal lead is a first signal lead, wherein the semiconductor package further comprises a second semiconductor die and a second signal lead, wherein the first and second semiconductor dies are each power transistor dies, wherein the first and second semiconductor dies are configured as a half-bridge circuit, wherein the power leads are configured as power connections to the half-bridge circuit, and wherein the first and second signal leads form signal connections to the half-bridge circuit.

11. The semiconductor package of claim 1 , wherein the lead adapter retention feature is formed by a notch that partially penetrates a thickness of the signal lead.

12. A semiconductor device assembly, comprising:
a semiconductor package comprising a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections to the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die;
a signal lead adapter comprising a sleeve that is configured to be fitted over an outer end of the signal lead, and
wherein the signal lead comprises a signal lead adapter retention feature that is configured to engage with the signal lead adapter so as to reach an interlocked position as the sleeve is fitted over an outer end of the signal lead.

13. The semiconductor device assembly of claim 12 , wherein the signal lead comprises a first outer face that extends towards the outer end of the signal lead, wherein the signal lead adapter retention feature comprises an engagement surface that forms an angled edge with the first outer face, wherein an interior region of the sleeve comprises a second engagement surface, and wherein the second engagement surface of the signal lead adapter and the engagement surface of the signal lead adapter retention feature mutually oppose one another in the interlocked position.

14. The semiconductor device assembly of claim 13 , wherein the engagement surface of the signal lead adapter retention feature forms a step-shaped transition between a wider part and a narrower part of the signal lead, and wherein the sleeve is configured to be fitted over the wider part until the signal lead adapter reaches the interlocked position.

15. The semiconductor device assembly of claim 13 , wherein the signal lead adapter retention feature comprises a notch in the first outer face of the signal lead, wherein the signal lead adapter comprises a protrusion that is correspondingly shaped as the notch, and wherein the notch comprises the engagement surface of the signal lead adapter retention feature, and wherein the protrusion comprises the second engagement surface of the signal lead adapter.

16. The semiconductor device assembly of claim 12 , wherein the signal lead adapter further comprises a mating interface that extends past the outer end of the signal lead when the signal lead adapter is in the interlocked position, and wherein the mating interface is configured to mate with and form an electrical connection with a circuit board connection pin.

17. The semiconductor device assembly of claim 16 , wherein the mating interface is any one of:
a cylindrical sleeve that is configured to insertably receive the circuit board connection pin;
a planar mating surface that is configured to be welded or soldered to a corresponding planar surface of the circuit board connection pin; and
a fastener receptacle that is configured to align with a corresponding fastener receptacle from the circuit board connection pin.

18. The semiconductor device assembly of claim 12 , further comprising a plurality of power lead adapters that are each configured to be mated with and form an electrical connection to one of the power leads.

19. The semiconductor device assembly of claim 18 , wherein the power lead adapters each comprise a mating interface, wherein the mating interface comprises a sleeve that is configured to be fitted over the one of the power leads, or a planar tab that is configured to be welded to the one of the power leads.

20. The semiconductor device assembly of claim 12 , wherein the semiconductor package further comprises a second semiconductor die, wherein the first and second semiconductor dies are each power transistor dies, wherein the first and second semiconductor dies are configured as a half-bridge circuit, wherein the power leads are configured as power connections to the half-bridge c

Assignees

• Infineon Technologies Ag

Inventors

• Pai Ajay Poonjal
• Karczewski Tino
• Lis Adrian

Classifications

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/464

  Additional interconnections in combination with leadframes · CPC title

• H10W70/424

  Cross-sectional shapes (H10W70/481 takes precedence) · CPC title

• H10W70/40

  Leadframes · CPC title