Method to create air gaps

Patent metadata

Field	Value
Publication number	US-12112980-B2
Application number	US-202117304697-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Feb 13, 2017
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

Tin oxide films are used to create air gaps during semiconductor substrate processing. Tin oxide films, disposed between exposed layers of other materials, such as SiO 2 and SiN can be selectively etched using a plasma formed in an H 2 -containing process gas. The etching creates a recessed feature in place of the tin oxide between the surrounding materials. A third material, such as SiO 2 is deposited over the resulting recessed feature without fully filling the recessed feature, forming an air gap. A method for selectively etching tin oxide in a presence of SiO 2 , SiC, SiN, SiOC, SiNO, SiCNO, or SiCN, includes, in some embodiments, contacting the substrate with a plasma formed in a process gas comprising at least about 50% H 2 . Etching of tin oxide can be performed without using an external bias at the substrate and is preferably performed at a temperature of less than about 100° C.

First claim

What is claimed is:

1. A method for creating an air gap on a semiconductor substrate, the method comprising:
(a) providing a semiconductor substrate having an exposed layer of a first material, an exposed layer of a second material, and an exposed layer of tin oxide positioned between the layer of the first material and the layer of the second material;
(b) selectively etching the exposed tin oxide relative to both the first and the second materials, and thereby forming a recessed feature between the first and second materials; and
(c) depositing a third material over the recessed feature without fully filling the recessed feature, and thereby forming the air gap between the layer of the first material and the layer of the second material.

2. The method of claim 1 , wherein the first material is selected from the group consisting of SiO 2 , SiC, SiN, SiOC, SiNO, SiCNO, and SiCN, and wherein the second material is selected from the group consisting of SiO 2 , SiC, SiN, SiOC, SiNO, SiCNO, and SiCN.

3. The method of claim 1 , wherein the first material and the second material are the same.

4. The method of claim 1 , wherein the third material is Sift.

5. The method of claim 1 , wherein (b) comprises exposing the semiconductor substrate to a plasma formed in a process gas comprising at least about 50% H 2 .

6. The method of claim 1 , wherein (b) comprises etching the exposed tin oxide using a hydrogen-containing plasma etch chemistry at a temperature of less than about 100° C.

7. The method of claim 1 , wherein the exposed layer of tin oxide residing between the layer of the first material and the layer of the second material has a width of between about 20-100 Å.

8. The method of claim 1 , further comprising, prior to (a):
forming a gate on the semiconductor substrate;
forming a layer of the first material over the semiconductor substrate, such that the first material covers both sidewalls and a top surface of the gate;
forming a tin oxide layer over the layer of the first material such that Tin oxide covers the first material both on the sidewalls and on the top surface of the gate;
forming a layer of the second material over the tin oxide layer, such that the second material covers the tin oxide both on the sidewalls and on the top surface of the gate; and
removing the second material from the horizontal surfaces of the substrate and thereby forming a structure provided in (a).

9. The method of claim 8 , wherein the first material is SiN and the second material is SiO 2 .

10. The method of claim 8 , wherein the gate comprises a high-k oxide.

11. The method of claim 8 , wherein the tin oxide is deposited to a thickness of between about 20-100 Å.

12. The method of claim 1 , further comprising:
applying photoresist to the semiconductor substrate;
exposing the photoresist to light;
patterning the photoresist and transferring the pattern to the substrate;
and selectively removing the photoresist from the substrate.

Assignees

• Lam Res Corp

Inventors

• Van Cleemput Patrick A
• Varadarajan Seshasayee
• Van Schravendijk Bart J

Classifications

• H10P72/0606

  Position monitoring, e.g. misposition detection or presence detection · CPC title

• H10P72/0421

  for drying etching · CPC title

• H10P50/285

  of materials not containing Si, e.g. PZT or Al2O3 · CPC title

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title