Framework for application driven exploration and optimization of hardware engines

Patent metadata

Field	Value
Publication number	US-12112202-B2
Application number	US-202016882640-A
Country	US
Kind code	B2
Filing date	May 25, 2020
Priority date	May 25, 2019
Publication date	Oct 8, 2024
Grant date	Oct 8, 2024

Abstract

A system and method for evaluating optimization of a hardware engine are described herein. In an example embodiment, a first operation of a desired application is performed using one or more hardware resources each associated with one or more task graphs of a plurality of task graphs. A first result is recorded from a first simulation based on a first task graph of the plurality of task graphs implemented using a first configuration of a first hardware resource associated with the first task graph. A second result is recorded from a second simulation based on a second task graph of the plurality of task graphs implemented using a second configuration of a second hardware resource associated with the second task graph. An interface is generated based on the first result and the second result for rendering by a display device.

First claim

What is claimed is:

1. A computer-implemented method comprising:
generating, by a processor, a first task graph corresponding to an application software and defining a functionality so as to generate a first result, wherein the first task graph comprises a first plurality of tasks each configured to be implemented by a first configuration of a first hardware resource, wherein the first configuration includes firmware held in a non-volatile memory device;
generating, by the processor, a second task graph corresponding to the application software and defining the functionality so as to generate a second result, wherein the second task graph comprises a second plurality of tasks each configured to be implemented by a second configuration of a second hardware resource, wherein the second configuration includes a hardware acceleration resource; and
changing a code associated with the application software based on a comparison of the first result associated with the first configuration of the first hardware resource and the second result associated with the second configuration of the second hardware resource.

2. The method of claim 1 , wherein the first task graph comprises a first input interface and a first output interface and the second task graph comprises a second input interface and a second output interface.

3. The method of claim 2 , wherein the first input interface matches the second input interface and the first output interface matches the second output interface.

4. The method of claim 1 , further comprising:
encapsulating one or more of the first the hardware resource and the second hardware resource into a hardware engine;
generating a hardware engine input interface and a hardware engine output interface for the hardware engine; and
mapping one or more operations associated with the application software to the hardware engine.

5. The method of claim 1 , further comprising changing a configuration of one or more of the first hardware resource and the second hardware resource based on the comparison of the first and second results.

6. The method of claim 5 , wherein one or more of the first and second configurations comprises one or more configurable attributes.

7. The method of claim 6 , wherein the one or more configurable attributes comprise one of core type, firmware designation, general purpose, special purpose, packet size, packet descriptor size, processing speed, operations-per-cycle, pipeline-depth, branch predictor, stochastic cache, or tightly coupled memory (TCM).

8. The method of claim 5 , wherein at least one of the first hardware resource or the second hardware resource comprises a processing element and a memory.

9. The method of claim 8 , wherein at least one of the first hardware resource or the second hardware resource further comprises one or more hardware resource interfaces.

10. The method of claim 1 , wherein the interface comprises digital representations of one or more of utilization data, resource utilization data, performance data, cost data, area data, timing data, resource analysis trace data, execution sequence trace data, resource instance trace data.

11. The method of claim 4 , further comprising:
receiving a result from one or more of the first plurality of tasks of the first task graph, or the second plurality of tasks of the second task graph, or the operation associated with the application software via interaction signals.

12. The method of claim 1 , further comprising:
receiving a configuration associated with at least one of the first hardware resource or the second hardware resource via interaction signals from a computing device prior to the generation of the first result and the second result.

13. The method of claim 1 , wherein the first result and the second result are performed concurrently.

14. The method of claim 1 , wherein the comparison of the first result and the second result provides information indicative of one or more of dependency and resource allocation.

15. The method of claim 1 further comprising:
enabling exploration of trade-offs between the implementation of the functionalities associated with the first task graph and the second task graph.

16. The method of claim 1 , wherein the first task graph and the second task graphs are subsets of a set of task graphs available for selection to provide optimal performance of the application software.

17. A system comprising a memory storing instructions and a processor, coupled with the memory and to execute the instructions, the instructions when executed causing the processor to:
generate a first task graph corresponding to an application software and defining a functionality so as to generate a first result, wherein the first task graph comprises a first plurality of tasks each configured to be implemented by a first configuration of a first hardware resource, wherein the first configuration includes firmware held in a non-volatile memory;
generate a second task graph corresponding to the application software and defining the functionality so as to generate a second result, wherein the second task graph comprises a second plurality of tasks each configured to be implemented by a second configuration of a second hardware resource, wherein the second configuration includes a hardware acceleration resource; and
change a code associated with the application software based on a comparison of the first result associated with the first configuration of the first hardware resource and the second result associated with the second configuration of the second hardware.

18. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:
generate a first task graph corresponding to an application software and defining a functionality so as to generate a first result, wherein the first task graph comprises a first plurality of tasks each configured to be implemented by a first configuration of a first hardware resource, wherein the first configuration includes firmware held in a non-volatile memory device; generate a second task graph corresponding to the application software and defining the functionality so as to generate a second result, wherein the second task graph comprises a second plurality of tasks each configured to be implemented by a second configuration of a second hardware resource, wherein the second configuration includes a hardware acceleration resource; and
change a code associated with the application software based on a comparison of the first result associated with the first configuration of the first hardware resource and the second result associated with the second configuration of the second hardware resource.

19. The non-transitory computer readable medium of claim 18 wherein the instructions further cause the processor to generate an input interface and an output interface for the first task graph.

Assignees

• Synopsys Inc

Inventors

• Garg Amit
• Tara Amit
• Deshpande Shripad

Classifications

• G06F9/50

  Allocation of resources, e.g. of the central processing unit [CPU] · CPC title

• G06F9/5061

  Partitioning or combining of resources · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F9/5066

  Algorithms for mapping a plurality of inter-dependent sub-tasks onto a plurality of physical CPUs (mappping at compile time, see G06F8/451) · CPC title