Testing and repair of a hardware accelerator image in a programmable logic circuit

Patent metadata

Field	Value
Publication number	US-9990212-B2
Application number	US-201314360657-A
Country	US
Kind code	B2
Filing date	Feb 19, 2013
Priority date	Feb 19, 2013
Publication date	Jun 5, 2018
Grant date	Jun 5, 2018

Abstract

Techniques described herein generally include methods for the testing and repair of a hardware accelerator image in a programmable logic circuit. In a processor chip that includes multiple programmable logic circuits, a hardware accelerator image programmed into a first programmable logic circuit is tested by programming a testing circuit with a duplicate hardware accelerator image and bringing the testing circuit to the same logic state as the first programmable logic circuit. Comparing outputs from the first programmable logic circuit and the testing circuit indicates the accuracy of the hardware accelerator image programmed into the first programmable logic circuit. The testing circuit may replace the first programmable logic circuit, or the testing circuit may be reprogrammed for testing other hardware accelerator images programmed into other programmable logic circuits of the processor chip.

First claim

I claim:

1. In a processor that includes multiple programmable logic circuits and that is configured to run an application, a method to manage operation of the multiple programmable logic circuits, the method comprising:
selecting a hardware accelerator image for duplication based on one or more of: time elapsed since the hardware accelerator image was last duplicated, a number of operations performed by the hardware accelerator image since being duplicated, and whether an error is experienced by a particular application associated with the hardware accelerator image;
duplicating the selected hardware accelerator image;
providing one or more inputs, associated with the application, to a first programmable logic circuit that is programmed with the selected hardware accelerator image;
monitoring outputs from the first programmable logic circuit, wherein the outputs from the first programmable logic circuit result from operation of the hardware accelerator image with the first programmable logic circuit using the one or more inputs associated with the application, and wherein the outputs from the first programmable logic circuit are used by the processor to run the application;
providing the one or more inputs, associated with the application, to a second programmable logic circuit that is programmed with the duplicate hardware accelerator image;
monitoring outputs from the second programmable logic circuit, wherein the outputs from the second programmable logic circuit result from operation of the duplicate hardware accelerator image with the second programmable logic circuit using the one or more inputs associated with the application;
comparing the outputs from the first programmable logic circuit with the outputs from the second programmable logic circuit;
based on the comparison of the outputs from the first programmable logic circuit with the outputs from the second programmable logic circuit, determining an operational status of the first programmable logic circuit and the second programmable logic circuit that have been programmed with the selected hardware accelerator image and the duplicate hardware accelerator image, respectively;
storing the determined operational status; and
using, by the processor, the outputs from the second programmable logic circuit to run the application in response to a determination that operation of the first programmable logic circuit is error-free.

2. The method of claim 1 , further comprising:
after determining the operational status of the second programmable logic circuit, programming the first programmable logic circuit with a different hardware accelerator image.

3. The method of claim 2 , wherein the application includes a first application, and wherein the different hardware accelerator image is associated with a second application that is being run by the processor.

4. The method of claim 1 , wherein the outputs from the second programmable logic circuit are used to run the application after the second programmable logic circuit has a same logic state as the first programmable logic circuit.

5. The method of claim 4 , wherein comparing the outputs from the first programmable logic circuit with the outputs from the second programmable logic circuit comprises determining the logic state of the second programmable logic circuit.

6. The method of claim 1 , further comprising placing the second programmable logic circuit to a same logic state as the first programmable logic circuit by providing a particular number of inputs to the second programmable logic circuit that are identical to the one or more inputs provided to the first programmable logic circuit.

7. The method of claim 1 , wherein providing the one or more inputs to the second programmable logic circuit is performed in response to detection of coupling of a computing device that includes the processor to a power supply external to the computing device.

8. The method of claim 1 , wherein providing the one or more inputs to the second programmable logic circuit is initiated in response to a determination by the processor that an error associated with the application has occurred.

9. The method of claim 1 , further comprising:
in response to a determination that the outputs from the first programmable logic circuit fail to match the outputs from the second programmable logic circuit, designating the determined operational status of the first programmable logic circuit as invalid for use.

10. The method of claim 9 , further comprising performing additional testing on the first programmable logic circuit.

11. The method of claim 1 , further comprising:
prior to providing the one or more inputs to the second programmable logic circuit, selecting the second programmable logic circuit from a plurality of programmable logic circuits, wherein the selection of the second programmable logic circuit is based on a number of times that the second programmable logic circuit has been reprogrammed.

12. The method of claim 1 , wherein the one or more inputs are provided to the first programmable logic circuit and the second programmable logic circuit at a first time, and wherein the method further comprises:
providing the one or more inputs to the first programmable logic circuit and the second programmable logic circuit for at least a second time;
monitoring outputs from the first programmable logic circuit and the second programmable logic circuit that respectively result from operation of the hardware accelerator image with the first programmable circuit and the duplicate hardware accelerator image with the second programmable logic circuit, using the one or more inputs for the at least second time; and
based on a comparison of the outputs from the first programmable logic circuit with the second programmable logic circuit that respectively result from the operation of the hardware accelerator image with the first programmable logic circuit and the duplicate hardware accelerator image with the second programmable logic circuit, using the one or more inputs for the at least second time, determining the operational status of at least one of the first programmable logic circuit and the second programmable logic circuit.

13. In a processor that includes multiple programmable logic circuits and that is configured to run an application, a method to manage operation of the multiple programmable logic circuits, the method comprising:
selecting a hardware accelerator image for duplication based on one or more of: time elapsed since the hardware accelerator image was last duplicated, a number of operations performed by the hardware accelerator image since being duplicated, and whether an error is experienced by a particular application associated with the hardware accelerator image;
duplicating the selected hardware accelerator image;
providing one or more inputs, associated with the application, to a first programmable logic circuit of the processor that is programmed with the selected hardware accelerator image;
monitoring outputs from the first programmable logic circuit, wherein the outputs from the first programmable logic circuit result from operation of the hardware accelerator image with the first programmable logic circuit using the one or more inputs associated with the application, and wherein the outputs from the first programmable logic circuit are used by the processor to run the application;
providing the one or more inputs to a second programmable logic circuit that is programmed with the duplicate hardware accelerator image;
monitoring outputs from the second programmable logic circuit, wherein the outputs from the second programmable logic circuit r

Assignees

• Empire Technology Dev Llc

Inventors

• Kruglick Ezekiel

Classifications

• G06F11/3409

  for performance assessment · CPC title

• G06F11/3024

  where the computing system component is a central processing unit [CPU] · CPC title

• G06F9/44505 Primary

  Configuring for program initiating, e.g. using registry, configuration files · CPC title

• G06F11/277

  with comparison between actual response and known fault-free response · CPC title

• G01R31/318519 Primary

  Test of field programmable gate arrays [FPGA] · CPC title