Successive approximation register based time-to-digital converter using a time difference amplifier

Patent metadata

Field	Value
Publication number	US-12107596-B2
Application number	US-202217961845-A
Country	US
Kind code	B2
Filing date	Oct 7, 2022
Priority date	Oct 7, 2022
Publication date	Oct 1, 2024
Grant date	Oct 1, 2024

Abstract

A successive approximation register based time-to-digital converter circuit with a time difference amplifier (TDA). A first TDA which applies a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first TDA, a second TDA which applies a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second TDA, and a finite state machine which sets another gain value, for a next step in a N step conversion until N steps are completed, in the first and the second TDAs based on a bit value from a previous step, wherein the bit value indicates, for a step, whether the first or second amplified time difference signal is ahead.

First claim

What is claimed is:

1. A N-bit successive approximation register based time-to-digital converter comprising:
a first delay circuit configured to delay a first input signal to generate a delayed first input signal;
a second delay circuit configured to delay a second input signal to generate a delayed second input signal;
a first programmable time difference amplifier configured to apply a gain value to the delay between the first input signal and the delayed first input signal to generate an amplified delayed first input signal, which is feedback to the first delay circuit and the first programmable time difference amplifier;
a second programmable time difference amplifier configured to apply a gain value to the delay between the second input signal and the delayed second input signal to generate an amplified delayed second input signal, which is feedback to the second delay circuit and the second programmable time difference amplifier;
a comparator configured to determine a bit value for a step in a N step conversion, the bit value based on which of the amplified delayed first input signal and the amplified delayed second input signal is in leading position; and
a finite state machine configured to set another gain value, for a next step in the N step conversion, in the first programmable time difference amplifier based on the determined bit value in a previous step and set another gain value in the second programmable time difference amplifier based on the determined bit value in the previous step,
wherein the N-bit successive approximation register based time-to-digital converter is configured to
determine a bit value for each step in the N step conversion; and
output a digital result based on each determined bit value in the N step conversion.

2. The circuit of claim 1 , wherein the first input signal and the second input signal are time domain signals.

3. The circuit of claim 1 , further comprising
a voltage-to-time converter configured to convert a first voltage input signal and a second voltage input signal to the first input signal and the second input signal.

4. The circuit of claim 1 , wherein each gain value in the first programmable time difference amplifier and each gain value in the second programmable time difference amplifier are binary weighted gain values.

5. The circuit of claim 1 , wherein each gain value set for each step in the N step conversion for the first programmable time difference amplifier is different from each gain value set for each step in the N step conversion for the second programmable time difference amplifier.

6. The circuit of claim 1 , the N-bit successive approximation register based time-to-digital converter configured to operate in a looping configuration, wherein multiple loops are made using a current gain value setting to meet a desired gain value in a step.

7. The circuit of claim 1 , wherein the finite state machine is further configured to forego setting the another gain value in the first programmable time difference amplifier and the another gain value in the second programmable time difference amplifier until the N-bit successive approximation register based time-to-digital converter completes a defined number of loops to meet a desired gain value in a step.

8. The circuit of claim 1 , wherein each of the first programmable time difference amplifier and the second programmable time difference amplifier further comprise a two-stage time latch.

9. The circuit of claim 1 , wherein each of the first programmable time difference amplifier and the second programmable time difference amplifier further comprise
a first time latch;
a second time latch connected to the first time latch;
a gain logic circuit connected to the first time latch and the second time latch; and
a digital gain controller connected to the first time latch and the second time latch, wherein the digital gain controller is configured to configure the first time latch, the second time latch, and the gain logic circuit to generate an amplified delayed input signal based on control information received from the finite state machine.

10. The circuit of claim 9 , wherein each of the first programmable time difference amplifier and the second programmable time difference amplifier further comprise a skew circuit configured to maintain a constant skew for each gain value.

11. A circuit comprising:
a first variable gain time difference amplifier configured to apply a gain value to a time difference between a first signal edge and a first delayed signal edge to generate a first amplified time difference signal, which is feedback to the first variable gain time difference amplifier;
a second variable gain time difference amplifier configured to apply a gain value to a time difference between a second signal edge and a second delayed signal edge to generate a second amplified time difference signal, which is feedback to the second variable gain time difference amplifier; and
a finite state machine configured to set another gain value, for a next step in a N step conversion until N steps are completed, in the first variable gain time difference amplifier based on a bit value from a previous step and set another gain value in the second variable gain time difference amplifier based on the bit value from the previous step, wherein the bit value indicates, for a step in the N step conversion, which of the first amplified time difference signal and the second amplified time difference signal is ahead.

12. The circuit of claim 11 , further comprising
a phase comparator configured to determine each bit value for each step in the N step conversion.

13. The circuit of claim 11 , wherein each gain value in the first variable gain time difference amplifier and each gain value in the second variable gain time difference amplifier are binary weighted gain values.

14. The circuit of claim 11 , wherein each gain value set for each step in the N step conversion for the first variable gain time difference amplifier is different from each gain value set for each step in the N step conversion for the second variable gain time difference amplifier.

15. The circuit of claim 11 , wherein the finite state machine is further configured to forego setting the another gain value in the first variable gain time difference amplifier and the another gain value in the second variable gain time difference amplifier until a defined number of loops is completed to meet a desired gain value in a step.

16. The circuit of claim 11 , wherein each of the first variable gain time difference amplifier and the second variable gain time difference amplifier further comprise a two-stage time latch.

17. The circuit of claim 11 , wherein each of the first variable gain time difference amplifier and the second variable gain time difference amplifier further comprise
a first time latch;
a second time latch connected to the first time latch;
a gain logic circuit connected to the first time latch and the second time latch; and
a digital gain controller connected to the first time latch and the second time latch, the digital gain controller configured to configure the first time latch, the second time latch, and the gain logic circuit to generate a desired gain value and an amplified time difference signal based on control information received from the finite state machine.

18. The circuit of claim 17 , wherein each of the first variable gain time difference amplifier and the second variable gain time difference amplifier further comprise
a skew logic circuit configured to maintain

Assignees

• Ciena Corp

Inventors

• Safi-Harab Mouna
• Shalmani Soheyl Ziabakhsh
• Aouini Sadok
• Ben-Hamida Naim

Classifications

• H03M1/504

  using pulse width modulation · CPC title

• H03M1/16

  with scale factor modification, i.e. by changing the amplification between the steps {(H03M1/141 takes precedence)} · CPC title

• H03M1/462 Primary

  Details of the control circuitry, e.g. of the successive approximation register · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title