Humidity control or aqueous treatment for EUV metallic resist

US12106961B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12106961-B2
Application numberUS-202217581671-A
CountryUS
Kind codeB2
Filing dateJan 21, 2022
Priority dateJul 16, 2021
Publication dateOct 1, 2024
Grant dateOct 1, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; and developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer. The first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for forming a semiconductor device, comprising: forming a material layer over a substrate; treating a surface of the material layer with water; applying a photoresist composition over the surface of the material layer, thereby forming a photoresist layer over the material layer; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer; developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer; and etching the material layer to remove portions of the material layer not covered by the patterned photoresist layer, wherein the first baking process and the second baking process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%. 2. The method of claim 1 , wherein the photoresist composition comprises an organometallic compound and a solvent. 3. The method of claim 2 , wherein the photoresist composition further comprises from 0.001% to 5% by weight of water relative to the solvent. 4. The method of claim 2 , wherein the solvent comprises 2-methoxyethyl ether, ethylene glycol monomethyl ether or propylene glycol monomethyl ether. 5. The method of claim 3 , wherein the photoresist composition further comprises one or more additives selected from an acid, a base, an alcohol, or combinations thereof. 6. The method of claim 5 , wherein the photoresist composition comprises from 0.00001% to 99% of the one or more additives relative to water. 7. The method of claim 1 , wherein the developer is water or a developer solution comprising a solvent and water, wherein the developer solution comprises from 0.00001% to 50% by weight of water. 8. The method of claim 1 , wherein the developer is a developer gas comprising water, wherein the developer gas comprises from 0.00001% to 50% by weight of water. 9. A method of forming a semiconductor device, comprising: depositing a photoresist layer on a material layer disposed on a substrate by applying a photoresist composition to the material layer, the photoresist composition comprising an organometallic compound, a solvent and water, wherein the photoresist composition comprises from 0.0001% to 5% by weight of water with respect to the solvent; performing a first baking process to the photoresist layer; performing a first cooling process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the photoresist layer comprising the pattern; performing a second cooling process to the photoresist layer; developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer; and etching the material layer using the patterned photoresist layer as an etch mask, wherein the first baking process, the first cooling process, the second baking process and the second cooling process are conducted under an ambient atmosphere having a humidity level ranging from 55% to 100%. 10. The method of claim 9 , further comprising introducing water to the material layer prior to depositing the photoresist layer. 11. The method of claim 10 , where introducing water to the material layer comprises rinsing a surface of the material layer with water or a liquid solution comprising a solvent and water. 12. The method of claim 10 , wherein introducing water to the material layer comprises treating a surface of the material layer with a water vapor. 13. The method of claim 9 , further comprising introducing water to the photoresist layer prior to or after each of the first baking process, the first cooling process, the second baking process and the second cooling process. 14. The method of claim 13 , where introducing water to the photoresist layer comprises rinsing a surface of the photoresist layer with water or a liquid solution comprising a solvent and water. 15. The method of claim 13 , wherein introducing water to the photoresist layer comprises treating a surface of the photoresist layer with a water vapor. 16. A method of forming a semiconductor device, comprising: (a) depositing a material layer on a substrate; (b) depositing a photoresist layer on the material layer; (c) performing a first baking process to the photoresist layer; (d) performing a first cooling process to the photoresist layer; (e) exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; (f) performing a second baking process to the photoresist layer comprising the pattern; (g) performing a second cooling process to the photoresist layer; and (h) developing the photoresist layer having the pattern therein using a developer, thereby forming a patterned photoresist layer, wherein water is introduced into each of steps (a)-(h). 17. The method of claim 16 , further comprising introducing a purging gas in at least one step of steps (a)-(h), wherein the purging gas has a humidity level from 0% to 100%. 18. The method of claim 17 , wherein the purging gas comprises a mixture of N 2 , CO 2 and air. 19. The method of claim 16 , wherein water is introduced at the first baking process, the first cooling process, the second baking process and the second cooling process by conducting the first baking process, the first cooling process, the second baking process and the second cooling process under an ambient atmosphere having a humidity level ranging from 55% to 100%. 20. The method of claim 16 , wherein water is introduced at depositing the photoresist layer by introducing water into a photoresist composition from which the photoresist layer is formed.

Assignees

Inventors

Classifications

  • characterised by their composition, e.g. multilayer masks or materials · CPC title

  • Photolithographic processes · CPC title

  • Liquid compositions therefor, e.g. developers · CPC title

  • Coating processes; Apparatus therefor (applying coatings to base materials in general B05; applying photosensitive compositions to base for photographic purposes G03C1/74) · CPC title

  • characterised by the solvents or agents facilitating spreading, e.g. tensio-active agents · CPC title

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What does patent US12106961B2 cover?
A method for forming a semiconductor device is provided. The method includes applying a photoresist composition over a substrate, thereby forming a photoresist layer over the substrate; performing a first baking process to the photoresist layer; exposing the photoresist layer to an extreme ultraviolet (EUV) radiation, thereby forming a pattern therein; performing a second baking process to the …
Who is the assignee on this patent?
Taiwan Semiconductor Mfg Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P76/2041. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Oct 01 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).