Self-calibration circuit for delta-sigma modulators, corresponding device and method

Patent metadata

Field	Value
Publication number	US-12101104-B2
Application number	US-202217721110-A
Country	US
Kind code	B2
Filing date	Apr 14, 2022
Priority date	Apr 22, 2021
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

First claim

The invention claimed is:

1. A device, comprising:
a delta-sigma modulator having:
an input node;
a quantizer;
a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer; and
a feedback network including a plurality of digital-to-analog converters, wherein in a quantizing mode of operation,
each of the plurality of digital-to-analog converters of the feedback network is coupled between an output of the quantizer and a respective integrator of the plurality of cascaded integrators; and
the delta-sigma modulator generates a digital signal at an output of the quantizer based on an analog input signal received at the input node; and

calibration circuitry coupled to the output of the quantizer, wherein in a calibration mode of operation,
a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators;
integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation;
the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence; and
the calibration circuitry generates an integrator calibration signal based on the digital test signal and a reference digital word.

2. The device of claim 1 , wherein the signal propagation path comprises:
a first adder having:
a first input coupled to the input node;
a second input coupled to an output of the first digital-to-analog converter; and
an output coupled to an input of the first integrator; and

a second adder having:
a first input coupled to an output of the first integrator; and
an output coupled to an input of a second integrator of the plurality of cascaded integrators, wherein in the quantizing mode of operation, a second input of the second adder is coupled to an output of a second digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network.

3. The device of claim 2 , wherein, in the calibration mode of operation, operation of the second digital-to-analog converter is disabled.

4. The device of claim 1 , wherein, in the quantization mode of operation, the digital-to-analog converters of the feedback network generate respective weighted analog replicas of the output of the quantizer.

5. The device of claim 1 , wherein the periodic alternated digital sequence is a pattern having a form −N, −N, +N, +N, where N is a defined digital value.

6. The device of claim 5 , wherein the signal including the periodic alternated digital sequence comprises a value N/2 followed by the periodic alternating digital sequence.

7. The device of claim 5 , wherein the quantizer has a sampling period and the periodic alternated digital sequence maintains the values −N or +N for a time equal to the sampling period.

8. The device of claim 1 , wherein the calibration circuitry comprises:
a modulator, which, in the calibration mode of operation, modulates the output of the quantizer with a square-wave signal, generating a modulated signal;
a moving average filter, which, in the calibration mode of operation, generates an average signal based on the modulated signal; and
a comparator, which in the calibration mode of operation, compares the average signal with a reference digital word, generating a difference signal.

9. The device of claim 8 , wherein, in the calibration mode of operation:
the quantizer has a sampling period, and
the square-wave signal has a period of twice the sampling period.

10. The device of claim 8 , wherein the calibration circuitry comprises a state machine, which, in the calibration mode of operation, generates the integrator calibration signal as a function of the difference signal.

11. The device of claim 1 , comprising a dither circuit coupled to an input of the signal propagation path, wherein the dither circuit, in the calibration mode of operation, generates a dither signal.

12. The device of claim 1 , wherein the signal propagation path comprises a chopping amplifier coupled to an input of the first integrator of the plurality of cascaded integrators.

13. The device of claim 1 , wherein, in the calibration mode of operation, trim values of the plurality of integrators are set based on the integrator calibration signal.

14. The device of claim 1 , comprising an integrated circuit including the delta-sigma modulator and the calibration circuitry.

15. A system, comprising:
a sensor;
a delta-sigma modulator coupled to the sensor, the delta-sigma modulator having:
a quantizer;
a signal propagation path including a plurality of cascaded integrators coupled between the sensor and the quantizer; and
a feedback network including a plurality of digital-to-analog converters, wherein in a quantizing mode of operation,
each of the plurality of digital-to-analog converters of the feedback network is coupled between an output of the quantizer and a respective integrator of the plurality of cascaded integrators; and
the delta-sigma modulator generates a digital signal at an output of the quantizer based on an analog input signal received from the sensor; and

calibration circuitry coupled to the output of the quantizer, wherein in a calibration mode of operation,
a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators;
integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation;
the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence; and
the calibration circuitry generates an integrator calibration signal based on the digital test signal and a reference digital word.

16. The system of claim 15 , wherein the periodic alternated digital sequence is a pattern having a form −N, −N, +N, +N, where N is a defined digital value.

17. The system of claim 16 , wherein the signal including the periodic alternated digital sequence comprises a value N/2 followed by the periodic alternating digital sequence.

18. The system of claim 15 , wherein the calibration circuitry comprises:
a modulator, which, in the calibration mode of operation, modulates the output of the quantizer with a square-wave signal, generating a modulated signal;
a moving average filter, which, in the calibration mode of operation, generates an average signal based on the modulated signal; and
a comparator, which in the calibration mode of operation, compares the average signal with a reference digital word, generating a difference signal.

19. The system of claim 18 , wherein, in the calibration mode of operation:
the quantizer has a sampling period, and
the square-wave signal has a period of twice the sampling period.

20. The system of claim 18 , wherein the calibration circuitry comprises a state machine, which, in a calibration mode of operation, generates the integrator calibration signal as a function of the difference signal.

21. A method, comprising:
operating a delta-sigma mo

Assignees

• St Microelectronics Srl

Inventors

• Modaffari Roberto
• Pesenti Paolo

Classifications

• H03M3/496

  Details of sampling arrangements or methods · CPC title

• H03M3/464

  Details of the digital/analogue conversion in the feedback path · CPC title

• H03M3/436

  characterised by the order of the loop filter, e.g. error feedback type · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M3/454

  with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage · CPC title