Semiconductor device, semiconductor device package, and manufacturing methods thereof

US12100928B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12100928-B2
Application numberUS-202318310106-A
CountryUS
Kind codeB2
Filing dateMay 1, 2023
Priority dateMar 27, 2018
Publication dateSep 24, 2024
Grant dateSep 24, 2024

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of manufacturing a semiconductor device includes: preparing a bottom plate having an upper surface and a lower surface, wherein the lower surface of the bottom plate comprises a reference part and one or more inclined surfaces that are inclined with respect to the reference part, an upper portion of the one or more inclined surfaces being positioned above the reference part, and wherein a thickness of the bottom plate at the reference part is greater than a thickness of the bottom plate at the upper portion of the one or more inclined surfaces; joining a frame member to the bottom plate, at least a part of the frame member being disposed directly above the one or more inclined surfaces, a linear expansion coefficient of the frame member being smaller than a linear expansion coefficient of the bottom plate; and fixing a semiconductor element to the bottom plate.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising, in this order: preparing a bottom plate having an upper surface and a lower surface, wherein the lower surface of the bottom plate comprises a reference part and one or more inclined surfaces that are inclined with respect to the reference part, an upper portion of the one or more inclined surfaces being positioned above the reference part, and wherein a thickness of the bottom plate at the reference part is greater than a thickness of the bottom plate at the upper portion of the one or more inclined surfaces; joining a frame member to the bottom plate, at least a part of the frame member being disposed directly above the one or more inclined surfaces, a linear expansion coefficient of the frame member being smaller than a linear expansion coefficient of the bottom plate; and fixing a semiconductor element to the bottom plate, wherein a height of the upper portion of the one or more inclined surfaces relative to the reference part in the step of fixing the semiconductor element is lower than a height of the upper portion of the one or more inclined surfaces relative to the reference part in the step of preparing the bottom plate, due to warpage that occurs in the bottom plate during the step of joining the frame member. 2. The method according to claim 1 , wherein: at least a portion of the reference part is disposed in a central part of the lower surface. 3. The method according to claim 1 , wherein: the lower surface of the bottom plate has a first side and a second side that oppose each other and a third side and a fourth side that oppose each other. 4. The method according to claim 3 , wherein: the one or more inclined surfaces are connected to at least one of the first side, the second side, the third side and the fourth side. 5. The method according to claim 1 , the method further comprising, after the step of fixing the semiconductor element, joining a lid to the frame member. 6. The method according to claim 1 , wherein, in the step of fixing the semiconductor element, the semiconductor element is a semiconductor laser element. 7. A method of manufacturing a semiconductor device package, the method comprising, in this order: preparing a bottom plate having an upper surface and a lower surface, wherein the lower surface of the bottom plate comprises a reference part and one or more inclined surfaces that are inclined with respect to the reference part, an upper portion of the one or more inclined surfaces being positioned above the reference part, and wherein a thickness of the bottom plate at the reference part is greater than a thickness of the bottom plate at the upper portion of the one or more inclined surfaces; and joining a frame member to the bottom plate, at least a part of the frame member being disposed directly above the one or more inclined surfaces, a linear expansion coefficient of the frame member being smaller than a linear expansion coefficient of the bottom plate, wherein a height of the upper portion of the one or more inclined surfaces relative to the reference part after the step of joining the frame member is lower than a height of the upper portion of the one or more inclined surfaces relative to the reference part in the step of preparing the bottom plate, due to warpage that occurs in the bottom plate during the step of joining the frame member. 8. The method according to claim 7 , wherein: at least a portion of the reference part is disposed in a central part of the lower surface. 9. The method according to claim 7 , wherein: the lower surface of the bottom plate has a first side and a second side that oppose each other and a third side and a fourth side that oppose each other. 10. The method according to claim 9 , wherein: the one or more inclined surfaces are connected to at least one of the first side, the second side, the third side and the fourth side.

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What does patent US12100928B2 cover?
A method of manufacturing a semiconductor device includes: preparing a bottom plate having an upper surface and a lower surface, wherein the lower surface of the bottom plate comprises a reference part and one or more inclined surfaces that are inclined with respect to the reference part, an upper portion of the one or more inclined surfaces being positioned above the reference part, and wherei…
Who is the assignee on this patent?
Nichia Corp, Shinko Electric Ind Co
What technology area does this patent fall under?
Primary CPC classification H10H20/8582. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 24 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).