Imaging device with improved short-wavelength sensitivity

US12100722B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12100722-B2
Application numberUS-201917250834-A
CountryUS
Kind codeB2
Filing dateSep 17, 2019
Priority dateSep 21, 2018
Publication dateSep 24, 2024
Grant dateSep 24, 2024

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

There is provided an imaging device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer formed on the first semiconductor layer and having an opposite conductivity type to the first semiconductor layer, a pixel separation portion that demarcates a pixel region including the first semiconductor layer and the second semiconductor layer, a first electrode connected to the first semiconductor layer from one surface side of the semiconductor substrate, and a metal layer connected to the second semiconductor layer from a light irradiation surface side which is the other surface of the semiconductor substrate and buried in the pixel separation portion in at least a part of the semiconductor substrate in a thickness direction.

First claim

Opening claim text (preview).

The invention claimed is: 1. An imaging device, comprising: a first semiconductor layer on a semiconductor substrate; a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer has an opposite conductivity type to the first semiconductor layer; a pixel separation portion configured to demarcate a pixel region including the first semiconductor layer and the second semiconductor layer; a first electrode connected to the first semiconductor layer from a first surface side of the semiconductor substrate; a metal layer connected to the second semiconductor layer from a light irradiation surface side which is a second surface side of the semiconductor substrate, wherein the metal layer is buried in the pixel separation portion in at least a part of the semiconductor substrate; and a second electrode connected to the second semiconductor layer from the light irradiation surface side, wherein the second electrode corresponds to a position of the pixel separation portion, and the metal layer is electrically connected to the second semiconductor layer via the second electrode. 2. The imaging device according to claim 1 , wherein the second electrode is along a periphery of the pixel region. 3. The imaging device according to claim 1 , wherein the second electrode is in a region of a part of a periphery of the pixel region. 4. The imaging device according to claim 3 , wherein the pixel region is a rectangular pixel region; and the second electrode is in at least one of four corners of the rectangular pixel region. 5. The imaging device according to claim 3 , wherein the second electrode is buried in a hole in the second semiconductor layer. 6. The imaging device according to claim 3 , wherein the second electrode and the metal layer are formed of the same material. 7. The imaging device according to claim 1 , further comprising: an insulation film along the pixel separation portion and the light irradiation surface side, wherein the second electrode is buried in an opening in the second semiconductor layer; and a specific region in which an end of the insulation film retreats more than a wall surface of the opening, wherein the specific region is filled with the second electrode. 8. The imaging device according to claim 1 , further comprising: an insulation film along the pixel separation portion; and a specific region in which an end of the insulation film retreats in a thickness direction of the pixel separation portion, wherein the specific region is filled with the second electrode. 9. The imaging device according to claim 1 , wherein a voltage for multiplying electrons is applied between the first electrode and the metal layer. 10. The imaging device according to claim 1 , further comprising a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer and the second semiconductor layer have the same conductivity type. 11. The imaging device according to claim 1 , wherein the second electrode is on an upper surface of the pixel separation portion. 12. The imaging device according to claim 1 , wherein the pixel separation portion and the second electrode have a planar shape of a grid shape surrounding a plurality of pixel regions, and the plurality of pixel regions comprises the pixel region.

Assignees

Inventors

Classifications

  • the potential barrier working in avalanche mode, e.g. avalanche photodiodes · CPC title

  • Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title

  • Interconnections · CPC title

  • Pixel isolation structures · CPC title

  • H10F39/802Primary

    Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US12100722B2 cover?
There is provided an imaging device including a first semiconductor layer formed on a semiconductor substrate, a second semiconductor layer formed on the first semiconductor layer and having an opposite conductivity type to the first semiconductor layer, a pixel separation portion that demarcates a pixel region including the first semiconductor layer and the second semiconductor layer, a first …
Who is the assignee on this patent?
Sony Semiconductor Solutions Corp
What technology area does this patent fall under?
Primary CPC classification H10F39/802. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 24 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).