Semiconductor image sensor structure having metal-filled trench contact

Patent metadata

Field	Value
Publication number	US-2017092669-A1
Application number	US-201615375764-A
Country	US
Kind code	A1
Filing date	Dec 12, 2016
Priority date	Sep 29, 2015
Publication date	Mar 30, 2017
Grant date	—

Abstract

An image sensor structure includes a region of semiconductor material having a first major surface and a second major surface. A pixel structure is within the region of semiconductor material and includes a plurality of doped regions and a plurality of conductive structures. A metal-filled trench structure extends from the first major surface to the second major surface. A first contact structure is electrically connected to a first surface of the conductive trench structure, and a second contact structure electrically connected to a second surface of the conductive trench structure. In one embodiment, the second major surface is configured to receive incident light.

First claim

What is claimed is:

1 . An image sensor device comprising:
a first semiconductor region having a first major surface and an opposed second major surface; a first dielectric region disposed adjacent the second major surface; a pixel structure disposed proximate to the first major surface; a conductive trench structure comprising:
a trench extending through the first semiconductor region to the first dielectric region; and
a conductive material within the trench, wherein the conductive material is electrically isolated from the first semiconductor region, and wherein the conductive material comprises a metal;
an insulated interconnect structure overlying the first major surface of the first semiconductor region, wherein the insulated interconnect structure is electrically coupled to a first side of the conductive trench structure; and a first electrode overlying the first dielectric region and electrically coupled to a second side of the conductive trench structure opposite to the first side, wherein the second major surface is configured to receive incident light.

2 . The device of claim 1 , wherein the pixel structure comprises:
a plurality of doped regions within the first semiconductor region adjacent the first major surface; and a plurality of conductive structures electrically coupled to the plurality of doped regions.

3 . The device of claim 2 further comprising:
a first dielectric layer over the plurality of conductive structures and the first semiconductor region, wherein trench extends through the first dielectric layer and the first semiconductor region to the first dielectric region, and wherein the insulated interconnect structure comprises:
a plurality of conductive contact structures within the first dielectric layer and electrically coupled to the plurality of conductive structures and the plurality of doped regions; and
a first conductive interconnect structure adjacent the first dielectric layer, wherein the first conductive interconnect structure is electrically coupled to the conductive material within the trench and electrically coupled to at least a portion of the plurality of conductive contact structures.

4 . The device of claim 3 further comprising:
a second dielectric layer overlying the first conductive interconnect structure and the first dielectric layer;
a top conductive structure overlying the second dielectric layer, the top conductive structure electrically coupled to the first conductive interconnect structure;
a third dielectric layer overlying the top conductive structure; and
a fourth dielectric layer overlying the third dielectric layer, wherein the fourth dielectric layer comprises a substantially planar outer surface.

5 . The device of claim 1 further comprising an anti-reflective coating layer disposed adjacent to the second major surface and laterally overlapping at least a portion of the pixel structure.

6 . The device of claim 1 , wherein:
a dielectric layer is disposed adjacent sidewall surfaces of the trench and separates the conductive material from the first semiconductor region; and the conductive material comprises tungsten.

7 . The device of claim 1 , wherein the first semiconductor region comprises:
a first semiconductor layer adjacent the first dielectric region; and a second semiconductor layer adjacent the first semiconductor layer, wherein the first semiconductor layer has a higher dopant concentration than the second semiconductor layer.

8 . The device of claim 7 , wherein the second semiconductor layer has a graded dopant profile.

9 . The device of claim 7 , wherein the second semiconductor layer has a thickness in range from about 3 microns to about 100 microns.

10 . The device of claim 7 , wherein the second semiconductor layer comprises:
a first portion proximate to the first major surface, wherein the first portion has a substantially uniform dopant profile; and a second portion proximate to the first semiconductor layer, wherein the second portion has a generally linearly increasing dopant profile as the second semiconductor layer approaches the first dielectric region.

11 . An image sensor device comprising:
a semiconductor substrate comprising a first dielectric region defining a first major surface of the semiconductor substrate and a first semiconductor region disposed adjacent the first dielectric region and defining a second major surface of the semiconductor substrate opposed to the first major surface; a plurality of doped regions disposed within the first semiconductor region adjacent the first major surface; a plurality of conductive gate structures adjacent to the first major surface and adjacent to at least portions of the plurality of doped regions, wherein the plurality of doped regions and the plurality of conductive gates comprise a pixel structure; a conductive trench structure extending through the first semiconductor region to the first dielectric region, wherein the conductive trench structure comprises a conductive material electrically isolated from the first semiconductor region, and wherein the conductive material comprises a metal; an insulated interconnect structure disposed adjacent the plurality of conductive gate structures, wherein the insulated interconnect structure is electrically coupled to a first surface of the conductive material; and a first electrode disposed adjacent the first dielectric region and electrically coupled to a second surface of the conductive material, wherein the first major surface of the semiconductor substrate is configured to receive incident light.

12 . The device of claim 11 further comprising:
a first dielectric layer interposed between the first plurality of conductive gate structures and the insulated interconnect structure, wherein the conductive trench structure extends through the first dielectric layer to the first dielectric region.

13 . The device of claim 12 , wherein the conductive trench structure comprises:
a trench extending through the first dielectric layer and the first semiconductor region to the first dielectric region; and a second dielectric layer lining at least sidewall surfaces of the trench, and wherein the conductive material adjoins the second dielectric layer.

14 . The device of claim 13 , wherein:
the insulated interconnect structure comprises a first conductive interconnect structure adjacent the first dielectric layer; and the first conductive interconnect structure is electrically coupled to the conductive material within the trench and electrically coupled to at least a portion of the plurality of conductive contact structures.

15 . The device of claim 11 further comprising an anti-reflective coating layer disposed adjacent the first major surface.

16 . A backside illuminated image sensor structure comprising:
a region of semiconductor material having a first major surface and a second major surface; a pixel structure within the region of semiconductor material adjacent the first major surface; a conductive trench structure extending from the first major surface to the second major surface, wherein the conductive trench structure comprises a metal material, and wherein the conductive trench structure has a first surface proximate to the first major surface of the region of semiconductor material and a second surface adjacent the second major surface of the region of semiconductor material; a first contact structure electrically coupled to the first surface of the conductive trench structure; and a second contact structure electrically coupled to the se

Assignees

• Semiconductor Components Ind Llc

Inventors

• Jerome Rick
• Price David T
• Hong Sungkwon C
• Grivna Gordon M

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/218

  in silicon-on-insulator [SOI] wafers · CPC title

• H10W20/2134

  TSVs extending from the semiconductor wafer into back-end-of-line layers · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title