Electrostatic protection circuit and manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-12100703-B2
Application number	US-202217897302-A
Country	US
Kind code	B2
Filing date	Aug 29, 2022
Priority date	Oct 23, 2017
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

Provided an electrostatic protection circuit. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. Orthographic projection(s) of a channel and/or a first electrode of the first transistor on a main surface of the array substrate is/are within an orthographic projection of the first signal line on the main surface of the array substrate.

First claim

What is claimed is:

1. An electrostatic protection circuit, comprising: at least one first transistor and at least one second transistor, wherein
a gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line;
a gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line;
wherein the first signal line and the second signal line are any two adjacent signal lines on an array substrate, and the first electrode and the second electrode are one of a source electrode and a drain electrode, respectively;
the first transistor meets at least one of following requirements:
an orthographic projection of a channel of the first transistor on a main surface of the array substrate is within an orthographic projection of the first signal line on the main surface of the array substrate, wherein the main surface is a surface of the array substrate with a largest area; and
an orthographic projection of the first electrode of the first transistor on the main surface of the array substrate is within an orthographic projection of the first signal line on the main surface of the array substrate.

2. The electrostatic protection circuit according to claim 1 , wherein the first transistor is a thin film transistor, and the first transistor meets one of following requirements:
the gate electrode of the first transistor is disposed in the same layer as the first signal line; and
the first electrode and the second electrode of the first transistor are disposed in the same layer as the first signal line.

3. The electrostatic protection circuit according to claim 1 , wherein the second transistor is a thin film transistor, and the second transistor meets one of following requirements:
the gate electrode of the second transistor is disposed in the same layer as the second signal line; and
the first electrode and the second electrode of the second transistor are disposed in the same layer as the second signal line.

4. The electrostatic protection circuit according to claim 1 , wherein the first transistor is a thin film transistor;
the first signal line comprises a first wire and a second wire which are disposed in different layers, and a lead portion of the first wire is connected to a lead portion of the second wire through a via hole disposed in a lead region;
the gate electrode of the first transistor consists of the lead portion of the first wire, the first electrode of the first transistor consists of the lead portion of the second wire, and the second electrode of the first transistor consists of a lead portion of the second signal line.

5. The electrostatic protection circuit according to claim 4 , wherein the second transistor is a thin film transistor;
the second signal line comprises a third wire and a fourth wire which are disposed in different layers, and a lead portion of the third wire is connected to a lead portion of the fourth wire through a via hole disposed in a lead region;
the gate electrode of the second transistor consists of the lead portion of the third wire, the first electrode of the second transistor consists of the lead portion of the fourth wire, and the second electrode of the second transistor consists of a lead portion of the first signal line.

6. The electrostatic protection circuit according to claim 5 , there is one of:
when both the first transistor and the second transistor are bottom-gate transistors, the second wire is located at a side of the first wire away from the array substrate, and the fourth wire is located at a side of the third wire away from the array substrate; or
when both the first transistor and the second transistor are top-gate transistors, the second wire is located at a side of the first wire close to the array substrate, and the fourth wire is located at a side of the third wire close to the array substrate.

7. The electrostatic protection circuit according to claim 1 , wherein a width to length ratio of a channel of each of the transistors is less than or equal to one quarter.

8. The electrostatic protection circuit according to claim 1 , wherein an orthographic projection of a channel of each of the transistors on the main surface of the array substrate has a meandering serpentine shape.

9. The electrostatic protection circuit according to claim 1 , wherein the second transistor meets at least one of following requirements:
an orthographic projection of a channel of the second transistor on the main surface of the array substrate is within an orthographic projection of the second signal line on the main surface of the array substrate; and
an orthographic projection of the first electrode of the second transistor on the main surface of the array substrate is within an orthographic projection of the second signal line on the main surface of the array substrate.

10. The electrostatic protection circuit according to claim 1 , wherein an orthographic projection of an end, close to a channel, of at least one of the first electrode and the second electrode of each of the transistors on the main surface of the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the channel, and an upper base of the trapezoid is close to the channel relative to a lower base thereof.

11. The electrostatic protection circuit according to claim 1 , wherein
an orthographic projection of an end, close to the first electrode, of a channel of each of the transistors on the main surface of the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the first electrode, and an upper base of the trapezoid is close to the first electrode relative to a lower base thereof; and
an orthographic projection of an end, close to the second electrode, of a channel of each of the transistors on the main surface of the array substrate is one of triangular and trapezoidal, a tip of the triangle faces the second electrode, and an upper base of the trapezoid is close to the second electrode relative to a lower base thereof.

12. The electrostatic protection circuit according to claim 11 , wherein both the first transistor and the second transistor are thin film transistor;
wherein the first signal line comprises a first wire and a second wire which are disposed in different layers, and a lead portion of the first wire is connected to a lead portion of the second wire through a via hole disposed in a lead region; and the second signal line comprises a third wire and a fourth wire which are disposed in different layers, and a lead portion of the third wire is connected to a lead portion of the fourth wire through a via hole disposed in a lead region;
the gate electrode of the first transistor consists of the lead portion of the first wire, the first electrode of the first transistor consists of the lead portion of the second wire, and the second electrode of the first transistor consists of a lead portion of the second signal line;
the gate electrode of the second transistor consists of the lead portion of the third wire, the first electrode of the second transistor consists of the lead portion of the fourth wire, and the second electrode of the second transistor consists of a lead portion of the first signal line; an orthographic projection of a channel of the first transistor on the array substrate and an orthographic projection of the first electrode of the first transistor on the array substrate are both within an orthographic projection of the first signal line on the array

Assignees

• Boe Technology Group Co Ltd

Inventors

• Long Chunping
• Qiao Yong
• Wu Xinyin

Classifications

• H10D89/811

  using FETs as protective elements · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/421

  having a particular composition, shape or crystalline structure of the active layer · CPC title

• H10D89/813 Primary

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title

• H10D86/471

  having different architectures, e.g. having both top-gate and bottom-gate TFTs · CPC title