Electrostatic protection circuit and manufacturing method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-11495594-B2
Application number	US-201816340186-A
Country	US
Kind code	B2
Filing date	Aug 2, 2018
Priority date	Oct 23, 2017
Publication date	Nov 8, 2022
Grant date	Nov 8, 2022

Abstract

An electrostatic protection circuit and a manufacturing method thereof, an array substrate, and a display device are provided. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line.

First claim

What is claimed is:

1. An electrostatic protection circuit, comprising: at least one first transistor and at least one second transistor, wherein
a gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line;
a gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line;
wherein the first signal line and the second signal line are any two adjacent signal lines on an array substrate, and the first electrode and the second electrode are one of a source electrode and a drain electrode, respectively;
an orthographic projection of an end, dose to a channel, of the first electrode and an orthographic projection of an end, dose to the channel, of the second electrode of each of the transistors on a main surface of the array substrate are both triangular,
wherein the main surface is a surface of the array substrate with a largest area; orthographic projections of an first end and an second end of the channel of each of the transistors on the main surface of the array substrate are triangular, wherein the first end is an end of the channel close to the first electrode, and the second end is an end of the channel close to the second electrode; and a tip, facing the first electrode, of the triangle corresponding to the first end of the channel is aligned with a tip, facing the first end of the channel, of the triangle corresponding to the end of the first electrode, and a tip, facing the second electrode, of the triangle corresponding to the second end of the channel is aligned with a tip, facing the second end of the channel, of the triangle corresponding to the end of the second electrode; and the first transistor meets at least one of the following requirements: an orthographic projection of a channel of the first transistor on the main surface of the array substrate is within an orthographic projection of the first signal line on the main surface of the array substrate; and an orthographic projection of the first electrode of the first transistor on the main surface of the array substrate is within an orthographic projection of the first signal line on the main surface of the array substrate.

2. The electrostatic protection circuit according to claim 1 , wherein the first transistor is a thin film transistor, and the first transistor meets one of the following requirements:
the gate electrode of the first transistor is disposed in the same layer as the first signal line; and
the first electrode and the second electrode of the first transistor are disposed in the same layer as the first signal line.

3. The electrostatic protection circuit according to claim 1 , wherein the second transistor is a thin film transistor, and the second transistor meets one of the following requirements:
the gate electrode of the second transistor is disposed in the same layer as the second signal line; and
the first electrode and the second electrode of the second transistor are disposed in the same layer as the second signal line.

4. The electrostatic protection circuit according to claim 1 , wherein the first transistor is a thin film transistor;
the first signal line comprises a first wire and a second wire which are disposed in different layers, and a lead portion of the first wire is connected to a lead portion of the second wire through a via hole disposed in a lead region;
the gate electrode of the first transistor consists of the lead portion of the first wire, the first electrode of the first transistor consists of the lead portion of the second wire, and the second electrode of the first transistor consists of a lead portion of the second signal line.

5. The electrostatic protection circuit according to claim 4 , wherein the second transistor is a thin film transistor;
the second signal line comprises a third wire and a fourth wire which are disposed in different layers, and a lead portion of the third wire is connected to a lead portion of the fourth wire through a via hole disposed in a lead region;
the gate electrode of the second transistor consists of the lead portion of the third wire, the first electrode of the second transistor consists of the lead portion of the fourth wire, and the second electrode of the second transistor consists of a lead portion of the first signal line.

6. The electrostatic protection circuit according to claim 5 ,
when both the first transistor and the second transistor are bottom-gate transistors, the second wire is located at a side of the first wire away from the array substrate, and the fourth wire is located at a side of the third wire away from the array substrate; or
when both the first transistor and the second transistor are top-gate transistors, the second wire is located at a side of the first wire close to the array substrate, and the fourth wire is located at a side of the third wire close to the array substrate.

7. The electrostatic protection circuit according to claim 5 , wherein the first wire further comprises a wire portion extending toward a peripheral region and the wire portion is connected to the lead portion of the first wire, or the second wire further comprises a wire portion extending toward a peripheral region and the wire portion is connected to the lead portion of the second wire; and
the third wire further comprises a wire portion extending toward a peripheral region and the wire portion is connected to the lead portion of the third wire, or the fourth wire further comprises a wire portion extending toward a peripheral region and the wire portion is connected to the lead portion of the fourth wire.

8. The electrostatic protection circuit according to claim 1 , wherein a width to length ratio of a channel of each of the transistors is less than or equal to one quarter.

9. The electrostatic protection circuit according to claim 1 , wherein an orthographic projection of a channel of each of the transistors on the main surface of the array substrate has a meandering serpentine shape.

10. The electrostatic protection circuit according to claim 1 , wherein the second transistor meets at least one of the following requirements:
an orthographic projection of a channel of the second transistor on the main surface of the array substrate is within an orthographic projection of the second signal line on the main surface of the array substrate; and
an orthographic projection of the first electrode of the second transistor on the main surface of the array substrate is within an orthographic projection of the second signal line on the main surface of the array substrate.

11. The electrostatic protection circuit according to claim 1 , wherein both the first transistor and the second transistor are thin film transistor;
wherein the first signal line comprises a first wire and a second wire which are disposed in different layers, and a lead portion of the first wire is connected to a lead portion of the second wire through a via hole disposed in a lead region; and the second signal line comprises a third wire and a fourth wire which are disposed in different layers, and a lead portion of the third wire is connected to a lead portion of the fourth wire through a via hole disposed in a lead region;
the gate electrode of the first transistor consists of the lead portion of the first wire, the first electrode of the first transistor consists of the lead portion of the second wire, and the second electrode of the first transistor consists of a lead portion of the second signal line;
the gate electrode of the sec

Assignees

• Boe Technology Group Co Ltd

Inventors

• Long Chunping
• Qiao Yong
• Wu Xinyin

Classifications

• H02H9/045

  adapted to a particular application and not provided for elsewhere · CPC title

• H01L27/0266

  Electricity · mapped topic

• H01L27/1222

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H01L27/0292 Primary

  Electricity · mapped topic