Semiconductor package structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-12100665-B2
Application number	US-202117527226-A
Country	US
Kind code	B2
Filing date	Nov 16, 2021
Priority date	Nov 24, 2020
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

The present invention provides a semiconductor package structure including a first stacked structure and a second stacked structure, which is stacked on the first stacked structure. The first stacked structure includes a first dielectric layer, a first power chip, a first conductive connecting element, a first conductive pillar and a first patterned conductive layer. The second stacked structure includes a second dielectric layer, a second power chip, a second conductive connecting element, a second conductive pillar, a second patterned conductive layer, and a third patterned conductive layer. The first power chip and the second power chip are stacked to provide a smaller volume semiconductor package structure, that the first power chip and the second power chip may be directly electrically connected through the circuit structure and may eliminate the related disadvantages of the lead frame. In addition, a manufacturing method of a semiconductor package structure is also disclosed.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
a first stacked structure, comprising:
a first dielectric layer, which has a first surface and a second surface arranged opposite to each other;
a first patterned conductive layer, which is embedded in the first dielectric layer, and one side of the first patterned conductive layer is exposed to the first surface of the first dielectric layer;
a first power chip, which has a first electrode layout and a second electrode layout opposite to each other, embedded in the first dielectric layer and bonded to the first patterned conductive layer in the first dielectric layer by the second electrode layout side through a first conductive adhesive layer, wherein the first electrode layout of the first power chip is provided with at least one first conductive connecting element, and one end of the first conductive connecting element being exposed to the second surface of the first dielectric layer; and
at least one first conductive pillar, which is embedded in the first dielectric layer, one end of which is connected to the first patterned conductive layer in the first dielectric layer, and the other end is exposed to the second surface of the first dielectric layer; and
a second stacked structure, which is stacked on the first stacked structure, comprising:
a second dielectric layer having a third surface and a fourth surface arranged opposite to each other, wherein the third surface being adjacent to the second surface of the first dielectric layer;
a second patterned conductive layer, which is embedded in the second dielectric layer, one side of which being exposed to the third surface of the second dielectric layer to connect the first conductive pillar and the first conductive connecting element;
a second power chip, which has a third electrode layout and a fourth electrode layout arranged opposite to each other, embedded in the second dielectric layer and bonded to the second patterned conductive layer in the second dielectric layer by the fourth electrode layout side through a second conductive adhesive layer, wherein the third electrode layout of the second power chip being provided with at least one second conductive connecting element and one end of the second conductive connecting element is exposed to the fourth surface of the second dielectric layer, in which the projections of the second power chip and the first power chip being overlapped in the stacking direction;
at least one second conductive pillar, which is embedded in the second dielectric layer, one end of which is connected to the second patterned conductive layer in the second dielectric layer, and the other end is exposed to the fourth surface of the second dielectric layer; and
a third patterned conductive layer, which is disposed on the fourth surface of the second dielectric layer and connected to the second conductive pillar and the second conductive connecting element.

2. The semiconductor package structure of claim 1 , wherein the first electrode layout and the third electrode layout each comprises a drain and a gate, and the second electrode layout and the fourth electrode layout each comprises a source.

3. The semiconductor package structure of claim 1 , wherein the first electrode layout and the third electrode layout each comprises a source, and the second electrode layout and the fourth electrode layout each comprises a drain and a gate.

4. The semiconductor package structure of claim 1 , wherein the first patterned conductive layer comprises a patterned conductive layer and an external conductive pillar layer, which are stacked on top of each other and electrically connected, wherein the external conductive pillar layer has a columnar shape, and one end is exposed to the first surface of the first dielectric layer.

5. The semiconductor package structure of claim 1 , further comprising: a control chip having an active surface and a non-active surface opposed to each other and embedded in the first dielectric layer and connected to the first patterned conductive layer with the non-active surface through the first conductive adhesive layer, wherein the active surface of the control chip is connected with the second patterned conductive layer through a plurality of first conductive connecting elements.

6. The semiconductor package structure of claim 1 , further comprising: a control chip having an active surface and a non-active surface opposed to each other and embedded in the second dielectric layer and connected to the second patterned conductive layer with the non-active surface through the second conductive adhesive layer, wherein the active surface of the control chip is connected with the third patterned conductive layer through a plurality of second conductive connecting elements.

7. A manufacturing method of a semiconductor package structure, comprising the following steps:
providing a carrying board;
forming a first patterned conductive layer on the carrying board;
providing a first power chip, which has a first electrode layout and a second electrode layout arranged opposite to each other, to bond to the first patterned conductive layer by the second electrode layout side through a first conductive adhesive layer;
forming at least one first conductive connecting element on the first electrode layout of the first power chip;
forming at least one first conductive pillar on the first patterned conductive layer;
forming a first dielectric layer to cover the first patterned conductive layer, the first power chip, and the first conductive pillar and exposing one end of the first conductive pillar and one end of the first conductive connecting element so as to form a first stacked structure on the carrying board;
forming a second patterned conductive layer on the first dielectric layer of the first stacked structure to connect the first conductive pillar and the first conductive connecting element;
providing a second power chip, which has a third electrode layout and a fourth electrode layout arranged opposite to each other, to bond to the second patterned conductive layer by the fourth electrode layout side through a second conductive adhesive layer, wherein the third electrode layout is provided with at least one second conductive connecting element, wherein the projections of the second power chip and the first power chip overlap in the stacking direction;
forming at least one second conductive connecting element on the third electrode layout of the second power chip;
forming at least one second conductive pillar on the second patterned conductive layer;
forming a second dielectric layer to cover the second patterned conductive layer, the second power chip, and the second conductive pillar and exposing one end of the second conductive pillar and one end of the second conductive connecting element;
forming a third patterned conductive layer on the second dielectric layer to connect the second conductive pillar and the second conductive connecting element so as to form a second stacked structure on the first stacked structure; and
removing the carrying board.

8. The manufacturing method of claim 7 , wherein the first electrode layout and the third electrode layout each comprises a drain and a gate, and the second electrode layout and the fourth electrode layout each comprises a source.

9. The manufacturing method of claim 7 , wherein the first electrode layout and the third electrode layout each comprises a source, and the second electrode layout and the fourth electrode layout each comprises a drain and a gate.

10. The manufacturing method of claim 7 , further comprising:
before the process of forming the first dielectric layer, providing a control chip

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che-Wei

Classifications

• H10W90/766

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00 Primary

  Package configurations · CPC title