Semiconductor device with through-substrate via and method of manufacturing a semiconductor device with through-substrate via

Patent metadata

Field	Value
Publication number	US-12100644-B2
Application number	US-201917415167-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 21, 2018
Publication date	Sep 24, 2024
Grant date	Sep 24, 2024

Abstract

An intermetal dielectric and metal layers embedded in the intermetal dielectric are arranged on a substrate of semiconductor material. A via hole is formed in the substrate, and a metallization contacting a contact area of one of the metal layers is applied in the via hole. The metallization, the metal layer comprising the contact area and the intermetal dielectric are partially removed at the bottom of the via hole in order to form a hole penetrating the intermetal dielectric and extending the via hole. A continuous passivation is arranged on sidewalls within the via hole and the hole, and the metallization contacts the contact area around the hole. Thus the presence of a thin membrane of layers, which is usually formed at the bottom of a hollow through-substrate via, is avoided.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a substrate of semiconductor material;
an intermetal dielectric on the substrate;
metal layers embedded in the intermetal dielectric;
a contact area of one of the metal layers;
a via hole in the substrate opposite the contact area;
a metallization arranged in the via hole, the metallization being in contact with the contact area; and
a passivation layer, the intermetal dielectric being arranged between the substrate and the passivation layer,
wherein
a hole is arranged in the intermetal dielectric, the hole forming an extension of the via hole,
a continuous passivation is arranged on sidewalls within the via hole and the hole,
the metallization is in contact with the contact area around the hole,
the via hole together with the hole extends completely through the semiconductor device, and
the passivation layer abutting the continuous passivation arranged on the sidewall within the hole.

2. The semiconductor device of claim 1 , wherein the metallization is arranged between the continuous passivation and the sidewalls of the via hole at least in places.

3. The semiconductor device of claim 1 , wherein an insulating layer is arranged on a sidewall of the via hole, and the metallization forms a layer on the insulating layer.

4. The semiconductor device of claim 1 , wherein the metallization comprises an inner diameter inside the via hole, the hole comprises an inner diameter parallel to the inner diameter of the metallization, and the inner diameter of the metallization is larger than the inner diameter of the hole.

5. The semiconductor device of claim 1 , wherein the metallization comprises an outer diameter inside the via hole, the hole comprises an inner diameter parallel to the outer diameter of the metallization, and the outer diameter of the metallization equals the inner diameter of the hole.

6. The semiconductor device of claim 1 , wherein
the continuous passivation is formed by a continuous passivation layer.

7. The semiconductor device of claim 1 , further comprising:
a passivation layer of the continuous passivation in the via hole,
a further passivation layer of the continuous passivation in the hole, and
the passivation layer of the continuous passivation abutting the further passivation layer of the continuous passivation.

8. The semiconductor device of claim 7 , further comprising:
a pedestal formed by the further passivation layer where the further passivation layer abuts the passivation layer.

9. A device comprising a semiconductor device according to claim 1 , the device being at least one of: a photonic device, high-frequency photonic device, 3D camera, structured light camera, time-of-flight camera, stereoscopic imaging device, CMOS imaging sensor, rolling shutter image sensor, line scan image sensor, camera module, lidar detector, ambient light sensor, colour sensor, proximity sensor, gesture sensor, device for optical character recognition or edge detection, photocopier, document scanner, spectral sensing device and spectrum analyzer.

10. A method of producing a semiconductor device, comprising:
arranging an intermetal dielectric and metal layers embedded in the intermetal dielectric on a bottom surface of a substrate of semiconductor material, the bottom surface facing an opposite surface;
forming a via hole in the substrate;
applying a metallization in the via hole, the metallization contacting a contact area of one of the metal layers;
applying a mask comprising an opening above the via hole;
forming a hole by partially removing the metallization, the metal layer comprising the contact area and the intermetal dielectric through the opening of the mask, the hole penetrating the intermetal dielectric and extending the via hole;
forming a continuous passivation on sidewalls within the via hole and the hole;
arranging a passivation layer on the intermetal dielectric opposite the bottom surface of the substrate; and
forming the continuous passivation abutting the passivation layer,
wherein the via hole together with the hole extends completely through the semiconductor device.

11. The method of claim 10 , wherein
the mask is applied at a side of the semiconductor device facing the bottom surface of the substrate, and
before the hole is formed, a further passivation layer is applied on the sidewall within the via hole, and
after the hole is formed, a further passivation layer is applied on the sidewall within the hole, the further passivation layers forming the continuous passivation.

12. The method of claim 10 , wherein
the mask is applied at a side of the semiconductor device facing an opposite surface of the substrate, and
after the hole is formed, a further passivation layer is applied on the sidewalls within the via hole and the hole to form the continuous passivation.

13. The method of claim 12 , wherein
before the hole is formed, a handling wafer is attached to the intermetal dielectric,
the further passivation layer is applied, a bottom portion of the further passivation layer covering an area of the handling wafer at the bottom of the hole, and
the bottom portion of the further passivation layer is removed using a further mask, which is applied at a side of the semiconductor device facing the opposite surface of the substrate.

14. The method of claim 12 , wherein
before the hole is formed, a handling wafer is attached to the intermetal dielectric,
the further passivation layer is applied, a bottom portion of the further passivation layer covering an area of the handling wafer at the bottom of the hole,
the handling wafer is removed, and
the bottom portion of the further passivation layer is removed from the side where the handling wafer was attached.

15. A method of producing a semiconductor device, comprising:
arranging an intermetal dielectric and metal layers embedded in the intermetal dielectric on a bottom surface of a substrate of semiconductor material, the bottom surface facing an opposite surface;
forming a via hole in the substrate;
applying a metallization in the via hole, the metallization contacting a contact area of one of the metal layers;
applying a mask comprising an opening above the via hole;
forming a hole by partially removing the metallization, the metal layer comprising the contact area and the intermetal dielectric through the opening of the mask, the hole penetrating the intermetal dielectric and extending the via hole; and
forming a continuous passivation on sidewalls within the via hole and the hole,
wherein
the via hole together with the hole extends completely through the semiconductor device,
the mask is applied at a side of the semiconductor device facing an opposite surface of the substrate,
after the hole is formed, a further passivation layer is applied on the sidewalls within the via hole and the hole to form the continuous passivation,
before the hole is formed, a handling wafer is attached to the intermetal dielectric,
the further passivation layer is applied, a bottom portion of the further passivation layer covering an area of the handling wafer at the bottom of the hole,
the handling wafer is removed, and
the bottom portion of the further passivation layer is removed from the side where the handling wafer was attached.

Assignees

• Ams Ag

Inventors

• Loeffler Bernhard
• Bodner Thomas
• Siegert Joerg

Classifications

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/023 Primary

  the interconnections being through-semiconductor vias · CPC title